nlnet_2019_standards.mdwn

   1 # NL.net proposal - 2019-10-046
   2
   3 ## Project name
   4
   5 The Libre RISC-V SoC, Formal Standards Development
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_standards>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 The Libre RISC-V SoC is a hybrid CPU, VPU and GPU which is being designed
  23 to be libre to the bedrock. When the hardware is transparently auditable,
  24 it can be trusted to not secretly compromise the software running on it.
  25
  26 With RISC-V being in its early infancy, however, Standards for Video
  27 Acceleration and 3D Graphics Acceleration do not yet exist.  These need
  28 to be written, proposed, formally ratified and Conformance Test Suites
  29 written and likewise ratified.
  30
  31 This takes a huge amount of time and coordinated collaboration, and is
  32 a necessary co-dependent task alongside the actual development of the
  33 processor itself.
  34
  35
  36 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  37
  38 Luke Leighton is an ethical technology specialist who has a consistent
  39 24-year track record of developing code in a real-time transparent
  40 (fully libre) fashion, and in managing Software Libre teams. He is the
  41 lead developer on the Libre RISC-V SoC.
  42
  43 # Requested Amount
  44
  45 EUR 50,000.
  46
  47 # Explain what the requested budget will be used for?
  48
  49 The improvements and additions to RISC-V Standards (known as Extensions)
  50 need to be written, reviewed thoroughly, justification for the features
  51 given, and then proposed.
  52
  53 There are several (see links at end) already in draft form. The primary
  54 one is the Vectorisation Standard. Additional Vector Operations is
  55 another. Transcendental operations (SIN, COS, LOG) another.
  56
  57 Once drafts have been agreed, a simulator can be developed. Next is some
  58 unit tests, and after that, some formal Compliance Tests.
  59
  60 Finally this can be submitted to the RISC-V Foundation for formal
  61 adoption.
  62
  63 Traveling expenses for presenting the standards to the RISC-V community
  64 at Libre Conferences as well as RISC-V Workshops are needed.
  65
  66 Writing up of papers on the core technology and discoveries behind the
  67 standards, for presentation at IEEE and other Computing Conferences.
  68 This to aid in understanding of the need for the Standards and to
  69 make adoption easier.
  70
  71 # Does the project have other funding sources, both past and present?
  72
  73 The initial proposal in November 2018 was for implementation of the
  74 actual processor, as well as writing a simulator and developing Kazan,
  75 the 3D Vulkan Driver. Purism began also sponsoring the overall project
  76 in mid 2019.
  77
  78 It was discovered only in September 2019 on an offchance comment from
  79 someone inside the (closed participation) RISC-V Foundation that RISC-V
  80 Standards require a full Conformance Compliance Test Suite as part
  81 of formal acceptance.  This easily doubles the workload of Standards
  82 Development and is in no way coverable by the initial 2018 proposal.
  83
  84 # Compare your own project with existing or historical efforts.
  85
  86 RISC-V is in its early infancy and has neither Extensions for 3D nor
  87 Video.  Most off the shelf commercial SoCs will use a special custom block
  88 for Video, and a separate GPU for 3D. Each of these, bring proprietary,
  89 is an attack vector for privacy subversion.
  90
  91 In this project, the CPU *is* the VPU and the GPU, so there is nothing to
  92 compare it against.  The full transparency of the Standards Development
  93 Process is a necessary prerequisite for being able to trust the end
  94 result.
  95
  96 ## What are significant technical challenges you expect to solve during the project, if any?
  97
  98 The key challenge will not be technical, it is a communications issue. The
  99 RISC-V Foundation operates as a closed ITU Style Standards Organisation,
 100 requiring effectively an NDA for participation, with negligeable
 101 transparency and zero accountability.
 102
 103 A two year protracted and persistent request for open participation
 104 and recognition of the value of the same is finally starting to get
 105 action taken.
 106
 107 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 108
 109 As mentioned in the 2018 submission, the Libre RISC-V
 110 SoC has a full set of resources for Libre Project Management and development:
 111 mailing list, bugtracker, git repository and wiki - all listed here:
 112 <https://libre-riscv.org/>
 113
 114 In addition, we have a Crowdsupply page
 115 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 116 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 117 all picked up the story.  The list is updated and maintained here:
 118 <https://libre-riscv.org/3d_gpu/>
 119
 120 # Extra info to be submitted
 121
 122 * <http://libre-riscv.org/3d_gpu/>
 123 * <https://nlnet.nl/project/Libre-RISCV/>
 124 * <https://libre-riscv.org/simple_v_extension/>
 125 * <https://libre-riscv.org/ztrans_proposal/>
 126 * <https://libre-riscv.org/zfpacc_proposal/>
 127 * Several other sub-proposals as part of the above.
 128
 129 # Management Summary
 130
 131 The Libre SoC was first funded from NLNet in 2018.  This was for the core
 132 of the project, based on an informally-developed Hybrid CPU-GPU 3D
 133 instruction set that had been written (and implemented in a simulator)
 134 in the 18 months prior to contacting NLNet.  During the implementation
 135 it became clear that a lot more work would be needed, and, further, that
 136 to meet proper transparency criteria, the proposed instruction set
 137 enhancements would need to be properly written up.  In addition,
 138 negotiations and communications with the Standards Body responsible
 139 for POWER ISA (the OpenPower Foundation) also needed to be taken into
 140 consideration.  Therefore this proposal was submitted so that full
 141 transparency and understanding of the Libre SoC is achieved.