nlnet_2019_video.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre-RISCV SoC, Video Decoding
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_video>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  23 modern processor, developed transparently and as libre to the bedrock
  24 as possible.
  25
  26 One of the main "hardware accelerated blocks" of any processor intended for user applications is Video Encode and Decode. This usually means an opaque, proprietary piece of hardware, and it usually comes with proprietary firmware as well.
  27
  28 In a privacy-respecting world neither of these are acceptable, therefore the goal is to develop - in an iterative fashion - not just the software but the actual hardware instructions (similar to ARM NEON) which, if fully integrated into libswscale, ffmpeg, gstreamer and other software, would make RISC-V a truly commercially competitive peer of ARM and x86 systems when it comes to video decode.
  29
  30 There would thus be no opportunity and no excuse for the inclusion of spying hardware blocks or coprocessors.
  31
  32 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  33
  34 Luke Leighton is an ethical technology specialist who has a consistent
  35 24-year track record of developing code in a real-time transparent
  36 (fully libre) fashion, and in managing Software Libre teams.  He is the
  37 lead developer on the Libre RISC-V SoC.
  38
  39
  40 # Requested Amount
  41
  42 EUR 50,000.
  43
  44 # Explain what the requested budget will be used for?
  45
  46 The tasks, which will need to be iteratively applied, are as follows:
  47
  48 * to identify closely the key areas in video decode, across a wide range of algorithms, where a non-accelerated processor spends considerable CPU time and power consumption.
  49 * to propose and then evaluate the instructions which, if included in RISC-V, would speed up video decode and reduce power consumption to within commercially competitive levels.
  50 * to simulate those proposed instructions and confirm their viability
  51 * to implement those instructions in actual hardware, for running in an FPGA
  52 * to follow through with the upstream submission and acceptance of customisation of relevant software libre video decode projects and toolchains.
  53
  54 This needs to be done iteratively because it is only when a certain high level of functionality is reached (FPGA, full simulation) will it be possible to properly determine if the proposed instructions actually meet the requirements.
  55
  56 # Does the project have other funding sources, both past and present?
  57
  58 The overall project has sponsorship from Purism as well as a prior grant
  59 from NLNet.  However that is for specifically covering the development
  60 of the RTL (the hardware source code).
  61
  62 There is no source of funds for the work on the
  63
  64 # Compare your own project with existing or historical efforts.
  65
  66 There are several Open VLSI Tool suites:
  67
  68 * GNU Electric: https://www.gnu.org/software/electric/
  69 * MAGIC: http://opencircuitdesign.com/magic/
  70 * The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
  71 * QFlow: http://opencircuitdesign.com/qflow/
  72 * Toped: http://www.toped.org.uk/
  73
  74 and a few more.  We choose Coriolis2 because of its python interface.
  75 The VLSI Layout is actually done as a *python* program.  With nmigen
  76 (the HDL) being in python, we anticipate the same OO benefits to be
  77 achievable in coriolis2 as well.
  78
  79 The case for the Libre RISC-V SoC itself was made already in the initial
  80 2018.02 proposal.  That has not changed: there are no Libre / Open Projects
  81 approaching anything like the complexity and product market opportunities
  82 of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
  83 multi-issue out-of-order design.  All other Libre / Open processors such
  84 as Raven, and many more, have a goal set in advance not to exceed around
  85 the 350mhz mark, and are single-core.
  86
  87 Other projects which are "open", such as the Ariane Processor, are
  88 developed by universities, and in the case of Ariane were *SPECIFICALLY*
  89 designed by and for the use of proprietary toolchains, such as those from
  90 Cadence, Synopsys and Mentor Graphics.  Despite the source code being
  91 "open", there was absolutely no expectation that the processor of the
  92 same capability as the Libre RISC-V SoC would use Libre / Open tools.
  93
  94 Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
  95 single-core and a maximum of around 350mhz, this is just the first
  96 stepping stone to a much larger processor.
  97
  98 ## What are significant technical challenges you expect to solve during the project, if any?
  99
 100 Some of these have been mentioned above:
 101
 102 * NDAs by Foundries may interfere with the ability for Chips4Makers to
 103   communicate with LIP6 regarding the necessary changes to NSXLIB which
 104   meet the TSMC Foundry "Design Rule Checks" (DRCs).
 105 * Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
 106   and the knock-on implications throughout the chain, right the way up
 107   to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
 108   be dealt with.
 109 * Circuit simulation and unit testing is going to be a major factor, and
 110   a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
 111   and high-end quad-core processors are going to be hopelessly inadequate.
 112
 113 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 114
 115 LIP6 have their own mailing list for the (transparent) discussion of
 116 issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
 117 SoC has a full set of resources for Libre Project Management and development:
 118 mailing list, bugtracker, git repository and wiki - all listed here:
 119 <https://libre-riscv.org/>
 120
 121 In addition, we have a Crowdsupply page
 122 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 123 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 124 all picked up the story.  The list is updated and maintained here:
 125 <https://libre-riscv.org/3d_gpu/>
 126
 127 # Extra info to be submitted
 128
 129 * <http://libre-riscv.org/3d_gpu/>
 130 * <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
 131 * <https://nlnet.nl/project/Libre-RISCV/>
 132 * <https://chips4makers.io/blog/>
 133