nlnet_2019_wishbone_streaming.mdwn

   1 # NL.net proposal
   2
   3 * NLNet Project Page <https://nlnet.nl/project/WishboneStreaming/>
   4
   5 ## Project name
   6
   7 The Libre RISC-V SoC, Wishbone Streaming Proposal
   8
   9 ## Website / wiki
  10
  11 <https://libre-riscv.org/nlnet_2019_wishbone_streaming>
  12
  13 Please be short and to the point in your answers; focus primarily on
  14 the what and how, not so much on the why. Add longer descriptions as
  15 attachments (see below). If English isn't your first language, don't
  16 worry - our reviewers don't care about spelling errors, only about
  17 great ideas. We apologise for the inconvenience of having to submit in
  18 English. On the up side, you can be as technical as you need to be (but
  19 you don't have to). Do stay concrete. Use plain text in your reply only,
  20 if you need any HTML to make your point please include this as attachment.
  21
  22 ## Abstract: Can you explain the whole project and its expected outcome(s).
  23
  24 In projects such as the Libre RISC-V SoC, commercial grade System-on-Chip
  25 (SoC) bus infrastructure is needed. Nowadays this often means AMBA AXI4,
  26 AXI4-lite or AXI4-Stream, all published by ARM Limited. The AXI family is
  27 "royality-free" and it is not only patented but its patent holder has
  28 begun denying licenses due to the US Trade War.
  29
  30 The main alternative with large adoption is Wishbone, which is an Open
  31 Standard in contrast to AXI. However Wishbone does not have a "streaming"
  32 capability, which is typically needed for high-throughput data pathes and
  33 interfaces, e.g. for video applications and High-Performance Computing
  34 (HPC).
  35
  36 Therefore this project will write up an enhancement to the Wishbone B4 SoC
  37 Bus, provide Reference Implementations and Bus Function Models (BFM) which
  38 easily allows unit tests for all Wishbone BFM users. For demonstration
  39 we like to implement an example peripheral (here, an audio interface, for
  40 the Libre RISC-V SoC) also. This demonstrations proves our concept also.
  41
  42 A secondary objective will be to seek out Reference Implementations for
  43 Wishbone Master and Slave, provide formal correctness proofs, and add
  44 additional example peripherals - non-streaming ones - as resources permit.
  45
  46 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  47
  48 Luke Leighton is an ethical technology specialist who has a consistent
  49 24-year track record of developing code in a real-time transparent
  50 (fully libre) fashion, and in managing Software Libre teams. He is the
  51 lead developer on the Libre RISC-V SoC.
  52
  53 Hagen Sankowski is a Senior ASIC Design Engineer, with 20-year Experiences
  54 thru the whole Design Flow, from Digital Entry (Verilog HDL, VHDL) to
  55 DSM Backend and back. He has FPGA knowledge for Xilinx, Altera, Lattice
  56 and MicroSemi. Inventor and Patentee for a FPGA structure. Open Source
  57 Evangelist, member of the LibreSilicon project Team also.
  58
  59 # Requested Amount
  60
  61 EUR 50,000.
  62
  63 # Explain what the requested budget will be used for?
  64
  65 Improve the Wishbone B4 Specification to add streaming capability,
  66 comparable to AXI4-Stream, and feed the improvements back into the
  67 current stewardship for next Wishbone release.
  68
  69 Design Reference Implementations in nmigen and (System-)Verilog, Bus
  70 Function Models and other functionality in SystemVerilog for verification
  71 with full unit tests aiming best code coverage.
  72
  73 Use some of the Libre RISC-V SoC peripherals as a test platform
  74 and demonstrator (I2S Audio Streaming) for the proposed standard
  75 modifications.
  76
  77 Traveling expenses for presenting the Wishbone improvements to the RISC-V
  78 community once at the annual ORConf in 2020.
  79
  80 As a secondary objective: seek out existing (non-streaming) Wishbone
  81 Master and Slave Bus implementations (or implement them if necessary),
  82 provide formal proof unit tests of their correctness, and add additional
  83 example peripherals.
  84
  85 # Does the project have other funding sources, both past and present?
  86
  87 The concept of extending Wishbone to have streaming capability is entirely
  88 new: it has no source of funding.
  89
  90 The Libre RISC-V SoC has funding from NLNet under a 2018 Grant: it was
  91 intending to use AXI4 prior to the U.S. Trade War.
  92
  93 # Compare your own project with existing or historical efforts.
  94
  95 AXI4 has streaming (as AXI4-Stream) but it is proprietary and patented.
  96
  97 TileLink is an alternative protocol (with roots in the RISC-V academic
  98 community) but it is relatively new, quite complex, and does not have
  99 the same adoption as Wishbone.
 100
 101 There do exist a number of pre-existing Wishbone Bus Master and
 102 Slave implementations: Wishbone has been around for a significantly
 103 long time and has been the de-facto choice in the Libre/Open Hardware
 104 community. Formal correctness proofs for Wishbone have been written by
 105 Dan Gisselquist in SystemVerilog, but none are written in nmigen.
 106
 107 ## What are significant technical challenges you expect to solve during the project, if any?
 108
 109 This is a straightforward project. However the timing issues involved
 110 with Bus Negotiation can be awkward to get right and may need formal
 111 proofs to properly verify.  Dan Gisselquist's work in his area shows
 112 how it can be done.
 113
 114 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 115
 116 As mentioned in the 2018 submission, the Libre RISC-V
 117 SoC has a full set of resources for Libre Project Management and development:
 118 mailing list, bugtracker, git repository and wiki - all listed here:
 119 <https://libre-riscv.org/>
 120
 121 In addition, we have a Crowdsupply page
 122 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 123 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 124 all picked up the story.  The list is updated and maintained here:
 125 <https://libre-riscv.org/3d_gpu/>
 126
 127 # Extra info to be submitted
 128
 129 * <http://libre-riscv.org/3d_gpu/>
 130 * <https://nlnet.nl/project/Libre-RISCV/>
 131 * <https://cdn.opencores.org/downloads/wbspec_b4.pdf>
 132 * <https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html>