nlnet_2019_wishbone_streaming.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre RISC-V SoC, Wishbone Streaming Proposal
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_wishbone_streaming>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 In projects such as the Libre RISCV SoC, commercial grade communications bus infrastructure is needed. Ordinarily this would mean AXI4 however it is not only patented but its patent holder has begun denying licenses due to the US trade war.
  23
  24 The main alternative with large adoption is Wishbone. However Wishbone does not have "streaming" capability, which is typically needed for audio and video streaming interfaces.
  25
  26 Therefore this project will write up an enhancement to the Wishbone B4 interface, provide Reference Implementations and unit tests, and also implement an example peripheral, an audio interface, for the Libre RISC-V SoC in order to prove the concept.
  27
  28 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  29
  30 Luke Leighton is an ethical technology specialist who has a consistent
  31 24-year track record of developing code in a real-time transparent
  32 (fully libre) fashion, and in managing Software Libre teams.  He is the
  33 lead developer on the Libre RISC-V SoC.
  34
  35 Hagen Sankowski is a Senior ASIC Design Engineer, with Experiences thru the whole Design Flow, from Digital Entry (Verilog HDL, VHDL) to DSM Backend and back.
  36 FPGA knowledge for Xilinx, Altera, Lattice and MicroSemi. Inventor and Patentee for a FPGA structure.
  37 Open Source Evangelist, always interested in challenging FPGA and migration projects.
  38
  39 # Requested Amount
  40
  41 EUR 50,000.
  42
  43 # Explain what the requested budget will be used for?
  44
  45 Improve the Wishbone B4 Specification to add streaming capability,
  46 similar to AXI4 Streams.
  47
  48 Design Reference Implementations in nmigen and verilog, with full unit tests.
  49
  50 Use some of the Libre RISC-V SoC peripherals as a test platform
  51 (I2S Audio Streaming) for the proposed standard modifications.
  52
  53 # Does the project have other funding sources, both past and present?
  54
  55 no.
  56
  57 # Compare your own project with existing or historical efforts.
  58
  59 AXI4 has streaming but it is proprietary and patented.
  60
  61 TileLink is the alternative protocol but it is relatively new, quite complex, and does not have the same adoption as Wishbone.
  62
  63 ## What are significant technical challenges you expect to solve during the project, if any?
  64
  65 This is a straightforward project. However the timing issues involved with Bus Negotiation can be awkward to get right and may need formal proofs to properly verify.
  66
  67 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
  68
  69 As mentioned in the 2018 submission, the Libre RISC-V
  70 SoC has a full set of resources for Libre Project Management and development:
  71 mailing list, bugtracker, git repository and wiki - all listed here:
  72 <https://libre-riscv.org/>
  73
  74 In addition, we have a Crowdsupply page
  75 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
  76 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
  77 all picked up the story.  The list is updated and maintained here:
  78 <https://libre-riscv.org/3d_gpu/>
  79
  80 # Extra info to be submitted
  81
  82 * <http://libre-riscv.org/3d_gpu/>
  83 * <https://nlnet.nl/project/Libre-RISCV/>