nlnet_2019_wishbone_streaming.mdwn

   1 # NL.net proposal
   2
   3 * NLNet Project Page <https://nlnet.nl/project/WishboneStreaming/>
   4 * 2019-10-043
   5
   6 ## Project name
   7
   8 The Libre RISC-V SoC, Wishbone Streaming Proposal
   9
  10 ## Website / wiki
  11
  12 <https://libre-riscv.org/nlnet_2019_wishbone_streaming>
  13
  14 Please be short and to the point in your answers; focus primarily on
  15 the what and how, not so much on the why. Add longer descriptions as
  16 attachments (see below). If English isn't your first language, don't
  17 worry - our reviewers don't care about spelling errors, only about
  18 great ideas. We apologise for the inconvenience of having to submit in
  19 English. On the up side, you can be as technical as you need to be (but
  20 you don't have to). Do stay concrete. Use plain text in your reply only,
  21 if you need any HTML to make your point please include this as attachment.
  22
  23 ## Abstract: Can you explain the whole project and its expected outcome(s).
  24
  25 In projects such as the Libre RISC-V SoC, commercial grade System-on-Chip
  26 (SoC) bus infrastructure is needed. Nowadays this often means AMBA AXI4,
  27 AXI4-lite or AXI4-Stream, all published by ARM Limited. The AXI family is
  28 "royality-free" and it is not only patented but its patent holder has
  29 begun denying licenses due to the US Trade War.
  30
  31 The main alternative with large adoption is Wishbone, which is an Open
  32 Standard in contrast to AXI. However Wishbone does not have a "streaming"
  33 capability, which is typically needed for high-throughput data pathes and
  34 interfaces, e.g. for video applications and High-Performance Computing
  35 (HPC).
  36
  37 Therefore this project will write up an enhancement to the Wishbone B4 SoC
  38 Bus, provide Reference Implementations and Bus Function Models (BFM) which
  39 easily allows unit tests for all Wishbone BFM users. For demonstration
  40 we like to implement an example peripheral (here, an audio interface, for
  41 the Libre RISC-V SoC) also. This demonstrations proves our concept also.
  42
  43 A secondary objective will be to seek out Reference Implementations for
  44 Wishbone Master and Slave, provide formal correctness proofs, and add
  45 additional example peripherals - non-streaming ones - as resources permit.
  46
  47 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  48
  49 Luke Leighton is an ethical technology specialist who has a consistent
  50 24-year track record of developing code in a real-time transparent
  51 (fully libre) fashion, and in managing Software Libre teams. He is the
  52 lead developer on the Libre RISC-V SoC.
  53
  54 Hagen Sankowski is a Senior ASIC Design Engineer, with 20-year Experiences
  55 thru the whole Design Flow, from Digital Entry (Verilog HDL, VHDL) to
  56 DSM Backend and back. He has FPGA knowledge for Xilinx, Altera, Lattice
  57 and MicroSemi. Inventor and Patentee for a FPGA structure. Open Source
  58 Evangelist, member of the LibreSilicon project Team also.
  59
  60 # Requested Amount
  61
  62 EUR 50,000.
  63
  64 # Explain what the requested budget will be used for?
  65
  66 Improve the Wishbone B4 Specification to add streaming capability,
  67 comparable to AXI4-Stream, and feed the improvements back into the
  68 current stewardship for next Wishbone release.
  69
  70 Design Reference Implementations in nmigen and (System-)Verilog, Bus
  71 Function Models and other functionality in SystemVerilog for verification
  72 with full unit tests aiming best code coverage.
  73
  74 Use some of the Libre RISC-V SoC peripherals as a test platform
  75 and demonstrator (I2S Audio Streaming) for the proposed standard
  76 modifications.
  77
  78 Traveling expenses for presenting the Wishbone improvements to the RISC-V
  79 community once at the annual ORConf in 2020.
  80
  81 As a secondary objective: seek out existing (non-streaming) Wishbone
  82 Master and Slave Bus implementations (or implement them if necessary),
  83 provide formal proof unit tests of their correctness, and add additional
  84 example peripherals.
  85
  86 # Does the project have other funding sources, both past and present?
  87
  88 The concept of extending Wishbone to have streaming capability is entirely
  89 new: it has no source of funding.
  90
  91 The Libre RISC-V SoC has funding from NLNet under a 2018 Grant: it was
  92 intending to use AXI4 prior to the U.S. Trade War.
  93
  94 # Compare your own project with existing or historical efforts.
  95
  96 AXI4 has streaming (as AXI4-Stream) but it is proprietary and patented.
  97
  98 TileLink is an alternative protocol (with roots in the RISC-V academic
  99 community) but it is relatively new, quite complex, and does not have
 100 the same adoption as Wishbone.
 101
 102 There do exist a number of pre-existing Wishbone Bus Master and
 103 Slave implementations: Wishbone has been around for a significantly
 104 long time and has been the de-facto choice in the Libre/Open Hardware
 105 community. Formal correctness proofs for Wishbone have been written by
 106 Dan Gisselquist in SystemVerilog, but none are written in nmigen.
 107
 108 ## What are significant technical challenges you expect to solve during the project, if any?
 109
 110 This is a straightforward project. However the timing issues involved
 111 with Bus Negotiation can be awkward to get right and may need formal
 112 proofs to properly verify.  Dan Gisselquist's work in his area shows
 113 how it can be done.
 114
 115 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 116
 117 As mentioned in the 2018 submission, the Libre RISC-V
 118 SoC has a full set of resources for Libre Project Management and development:
 119 mailing list, bugtracker, git repository and wiki - all listed here:
 120 <https://libre-riscv.org/>
 121
 122 In addition, we have a Crowdsupply page
 123 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 124 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 125 all picked up the story.  The list is updated and maintained here:
 126 <https://libre-riscv.org/3d_gpu/>
 127
 128 # Extra info to be submitted
 129
 130 * <http://libre-riscv.org/3d_gpu/>
 131 * <https://nlnet.nl/project/Libre-RISCV/>
 132 * <https://cdn.opencores.org/downloads/wbspec_b4.pdf>
 133 * <https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html>