nlnet_2019_wishbone_streaming.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre RISC-V SoC, Wishbone Streaming Proposal
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_wishbone_streaming>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 In projects such as the Libre RISCV SoC, commercial grade communications
  23 bus infrastructure is needed. Ordinarily this would mean AXI4 however
  24 it is not only patented but its patent holder has begun denying licenses
  25 due to the US trade war.
  26
  27 The main alternative with large adoption is Wishbone. However Wishbone
  28 does not have "streaming" capability, which is typically needed for
  29 audio and video streaming interfaces.
  30
  31 Therefore this project will write up an enhancement to the Wishbone B4
  32 interface, provide Reference Implementations and unit tests, and also
  33 implement an example peripheral, an audio interface, for the Libre RISC-V
  34 SoC in order to prove the concept.
  35
  36 A secondary objective will be to seek out Reference Implementations for
  37 Wishbone Master and Slave, provide formal correctness proofs, and add
  38 additional example peripherals - non-streaming ones - as resources permit.
  39
  40 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  41
  42 Luke Leighton is an ethical technology specialist who has a consistent
  43 24-year track record of developing code in a real-time transparent
  44 (fully libre) fashion, and in managing Software Libre teams.  He is the
  45 lead developer on the Libre RISC-V SoC.
  46
  47 Hagen Sankowski is a Senior ASIC Design Engineer, with Experiences
  48 thru the whole Design Flow, from Digital Entry (Verilog HDL, VHDL)
  49 to DSM Backend and back.  FPGA knowledge for Xilinx, Altera, Lattice
  50 and MicroSemi. Inventor and Patentee for a FPGA structure.  Open Source
  51 Evangelist, always interested in challenging FPGA and migration projects.
  52
  53 # Requested Amount
  54
  55 EUR 50,000.
  56
  57 # Explain what the requested budget will be used for?
  58
  59 Improve the Wishbone B4 Specification to add streaming capability,
  60 similar to AXI4 Streams.
  61
  62 Design Reference Implementations in nmigen and verilog, with full unit tests.
  63
  64 Use some of the Libre RISC-V SoC peripherals as a test platform
  65 (I2S Audio Streaming) for the proposed standard modifications.
  66
  67 As a secondary objective: seek out existing (non-streaming) Wishbone
  68 Master and Slave Bus implementations (or implement them if necessary),
  69 provide formal proof unit tests of their correctness, and add additional
  70 example peripherals.
  71
  72 # Does the project have other funding sources, both past and present?
  73
  74 The concept of extending Wishbone to have streaming capability is entirely
  75 new: it has no source of funding.
  76
  77 The Libre RISC-V SoC has funding from NLNet under a 2018 Grant: it was
  78 intending to use AXI4 prior to the U.S. Trade War.
  79
  80 # Compare your own project with existing or historical efforts.
  81
  82 AXI4 has streaming but it is proprietary and patented.
  83
  84 TileLink is the alternative protocol but it is relatively new, quite
  85 complex, and does not have the same adoption as Wishbone.
  86
  87 There do exist a number of pre-existing Wishbone Bus Master and Slave
  88 implementations: Wishbone has been around for a significantly long time
  89 and has been the de-facto choice in the Libre/Open Hardware community.
  90 Formal correctness proofs for Wishbone have been written by Dan Gisselquist
  91 in verilog, but none are written in nmigen.
  92
  93 ## What are significant technical challenges you expect to solve during the project, if any?
  94
  95 This is a straightforward project. However the timing issues involved
  96 with Bus Negotiation can be awkward to get right and may need formal
  97 proofs to properly verify.
  98
  99 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 100
 101 As mentioned in the 2018 submission, the Libre RISC-V
 102 SoC has a full set of resources for Libre Project Management and development:
 103 mailing list, bugtracker, git repository and wiki - all listed here:
 104 <https://libre-riscv.org/>
 105
 106 In addition, we have a Crowdsupply page
 107 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 108 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 109 all picked up the story.  The list is updated and maintained here:
 110 <https://libre-riscv.org/3d_gpu/>
 111
 112 # Extra info to be submitted
 113
 114 * <http://libre-riscv.org/3d_gpu/>
 115 * <https://nlnet.nl/project/Libre-RISCV/>
 116 * <https://cdn.opencores.org/downloads/wbspec_b4.pdf>
 117 * <https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html>