nlnet_2021_lip6_vlsi.mdwn

   1 # NLnet LIP6 VLSI Project Grant
   2
   3 * Code:         2021-08-049
   4
   5 ## Project name
   6
   7 LIP6 VLSI Tools
   8
   9 ## Website / wiki
  10
  11 <https://libre-soc.org/nlnet_2021_lip6_vlsi>
  12
  13 Please be short and to the point in your answers; focus primarily on
  14 the what and how, not so much on the why. Add longer descriptions as
  15 attachments (see below). If English isn't your first language, don't
  16 worry - our reviewers don't care about spelling errors, only about
  17 great ideas. We apologise for the inconvenience of having to submit in
  18 English. On the up side, you can be as technical as you need to be (but
  19 you don't have to). Do stay concrete. Use plain text in your reply only,
  20 if you need any HTML to make your point please include this as attachment.
  21
  22 ## Abstract: Can you explain the whole project and its expected outcome(s).
  23
  24 LIP6's VLSI tools are one of the few user-operated toolchains for creating
  25 ASIC layouts where the full source code is available for inspection.
  26 This means that there is no opportunity for insertion of rogue hardware
  27 into an ASIC made by LIP6 tools which could compromise user trust, either locally or for
  28 internet use. Further: academic, public and free discussion are all
  29 engendered and fostered where at present NDAs rife through the VLSI
  30 Industry prevent and prohibit discussion and general improvements beneficial
  31 to users.
  32
  33 The expected outcome is to improve Coriolis2, HITAS/YAGLE and extend the
  34 whole toolchain so that it is faster, able to handle larger ASIC designs,
  35 and can perform Logical Validation. Also to be improved and tested is
  36 support for lower geometries (starting with 130nm)
  37
  38 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  39
  40 LIP6 has created the ASIC Layout for the Libre-SOC 180nm ASIC that went to
  41 IMEC TSMC MPW in June 2021.  It was developed entirely with Libre source code
  42 from HDL to GDS-II, the only NDA being the TSMC PDK.
  43
  44
  45 # Requested Amount
  46
  47 EUR $50,000.
  48
  49 # Explain what the requested budget will be used for?
  50
  51 To improve the speed of the GUI front-end, to make it possible to
  52 handle larger ASIC designs, to add LVS capability, improve the internal
  53 data format (to better handle mixed case module and signal names), integrate
  54 the Static Timing Analysis tool (HITAS) and YAGLE gate-level extraction tool, to complete the conversion
  55 to python 3,
  56 to try smaller geometry ASICs (beginning with 130nm), and potentially
  57 investigate using multi-processing to speed up completion.
  58
  59 # Does the project have other funding sources, both past and present?
  60
  61 LIP6 is part of Sorbonne University.  The developers and maintainers
  62 of Coriolis2, HITAS/TAGLE, and Alliance, are all employed by Sorbonne
  63 University. For the Libre-SOC 180nm ASIC development an NLnet Grant
  64 was received, most of this work is now completed.
  65
  66 # Compare your own project with existing or historical efforts.
  67
  68 The only other major proven VLSI Toolchain that is Libre Licensed and
  69 has created successful ASICs is Magic, selected as part of the OpenROAD
  70 toolchain.  The entire OpenROAD toolchain is based on tcl/tk, a late 1980s
  71 scripting language technology.  LIP6 VLSI tools are written in c++ and python,
  72 which are modern much better well-known programming languages. With python
  73 being so well-known and prevalent it is much easier to operate and
  74 coriolis2
  75 for the development of complex reproducible ASIC layouts.
  76
  77 ## What are significant technical challenges you expect to solve during the project, if any?
  78
  79 The size of databases for VLSI ASIC Layout are extremely large, and a huge
  80 amount of computing power is needed, in one single machine.  In addition
  81 a huge amount of specialist knowledge of VLSI and silicon is needed,
  82 completely separately from actual Software Engineering skills. These
  83 three factors combine to really tax the development of VLSI tools.
  84
  85 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
  86
  87 The entire source code is developed and available immediately, through LIP6
  88 online resources including gitlab instance, mailing list, and website.
  89 Sorbonne University and LIP6 both have twitter accounts, and the developers
  90 write Academic papers and present at conferences.  In addition, they work
  91 with the Libre-SOC Team to promote milestones and developments.
  92
  93 # Extra info to be submitted
  94
  95 # Questions 01 Oct 2020
  96
  97 **What rates were used, and what main tasks are there**
  98
  99 we estimate the rates based on LIP6 University hiring an additional engineer in France, at commercial rates, to be around EUR 3000 to 4000 a month.
 100
 101 * training a new Engineer on coriolis2 c++/python internals: estimated
 102   2 months
 103 * porting to python3 estimated 2 months (some libraries have to be removed and rewritten) including re-running several designs and checking they are still the same.
 104 * porting and updating of older (Alliance) layout extractor tools
 105   (solstice, equinox) to newer (c++/python) coriolis2 as pure
 106   netlist extractor: 2 months
 107 * adding limited electrical information extraction (wire resistance
 108   and capacitance) to the new layout extractor: 4-6 weeks
 109 * researching Logical Equivalence algorithms and Academic papers to ensure good knowledge before proceeding: 4 to 5 weeks.
 110 * implementation of Logical Equivalence checker: 10 to 14 weeks.
 111   this is **not** the same as an **extraction** tool (above). the LEQ tool
 112   **uses** (checks) the extracted database.
 113 * validation of Logical Equivalence checker against simulations and other (proprietary) checkers: 5 to 7 weeks
 114 * Identifying locations in 150,00 lines of code which can be parallelised by "divide and conquer", and those which can be "threaded": 3 weeks
 115 * separation of code into separate processes ("divide and conquer"): 2 months
 116 * adding "mutex" (exclusion) protection around code which can be "threaded": 2 months
 117 * debugging and stabilising of both of the above: 2 months.
 118 * alternative file formats and data structures which support case-sensitive net names: 2 months
 119 * HITAS/YAGLE integration into coriolis2, updating license and documentation: 2 months
 120
 121 **You mention you will be able to perform Logical Validation.
 122 Can you expand a bit on that, what assurances could that bring?**
 123
 124 Short summary:
 125
 126 there are two main ways to check that the HDL matches (is "equivalent") with the transistor layout, which has many changes made:
 127
 128 1) simulation.  for large designs this requires supercomputers for months and sometimes years to complete the simulation.  realistically, only a
 129 very small number of cycles can be run (several days to run one "clock" cycle).
 130
 131 2) Formal Mathematical "Logical equivalence".  this performs boolean logic analysis and takes only hours (or days for very large designs).
 132
 133 it is extremely important for a professional VLSI toolchain to have this capability.
 134
 135 Longer version:
 136
 137 As I assume you are not familiar with making ASIC, I will try to
 138 explain with sufficient details while not being too long.
 139
 140 * The Place & Route (P&R) step of making an ASIC takes in input,
 141   you can think of it as a "specification", a netlist.
 142 * A netlist is, or can be understood as:
 143    1. A specialized kind of electrical schematic with (in digital
 144      cases) all components being 1 bit memories or boolean functions
 145      (AND, OR, NOR, ...).
 146    2. A gigantic automaton, or set of big boolean equations.
 147      The fact that all the components are either memories or logical
 148      functions enable that.
 149 * Checking that the P&R has worked correctly amount to re-create
 150   a netlist *from* the layout generated by the router. And, then,
 151   perform a comparison of the *specification* netlist and the
 152   one coming from the layout. Of course, they must be identical...
 153   This is a "simple" graph comparison.
 154 * BUT, during the P&R, to meet electrical constraints like timing or
 155   good power supply, the specification netlist *is modified*.
 156   For example, the clock is split into a clock-tree to ensure
 157   synchronicity all over the design or some very long wire is
 158   broken into smaller ones. In some cases, more drastic operations
 159   can be performed, like completely changing the way the boolean
 160   computations are done.
 161 * So, after extraction, we end up with two *different* netlists,
 162   which *should* implement the same automaton, hence the concept
 163   of "logical equivalence" (LEQ).
 164 * Currently, with Alliance/Coriolis, we check that the *modificated*
 165   netlist is identical to the one extracted from the layout.
 166   But we don't know with mathematical certainty that the
 167   *modificated* one is equivalent (not equal) to the specification
 168   one.
 169   Of course we have made some other tests to check that (pattern
 170   simulation) but it's not foolproof (to have good coverage the
 171   number of pattern grows in 2^N where N is the number of memory
 172   *bits* in the circuit...).