3 Current diagram for ongoing grant, no changes made anywhere.
5 Bug 961 - NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU TBD) - 100000
7 |-| (IN PROGRESS) Bug 737 - in-order single-issue Power ISA 3.0 core - 7000
8 | |- (NOT STARTED) Bug 1036 - Formal Proof for LDSTCompUnit is needed - 3000
9 | |- (DONE) Bug 1073 - Microwatt verilator sim - setting up chroot and documentation - 750
10 | |- (NOT STARTED) Bug 1149 - simplify the in-order core "multi-bit-masks" down to a single bit-vector - 3250
12 |-- (DONE) Bug 999 - SFFS Operating System Porting - 10000
14 |-| (IN PROGRESS) Bug 1003 - instruction database continuation and binutils, SVP64 - 10500
15 | |- (DONE) Bug 1068 - add instructions from ls012 not currently implemented in binutils - 3800
16 | |- (IN PROGRESS) Bug 1079 - make LD/ST-with-update EXTRA3 - 2000
17 | |- (ABSOLUTE TOP PRIORITY TO BE COMPLETED AS ABOLUTE CRITICAL WORK) Bug 1083 - update to DD FFirst Mode binutils PowerDecoder - 700
18 | | Comment #13 REQUESTS cancelling BUT IS DENIED AND NOT AUTHORIZED.
19 | |- (DONE) Bug 1094 - insndb instruction database visitor-walker is needed - 4000
21 |-- (NOT STARTED) Bug 1024 - Second phase of nmigen Dynamic Partitioned SIMD and nmigen language improvements - 6000
23 |-| (IN PROGRESS) Bug 1026 - implement Draft Instructions in nmigen HDL - 8000
24 | |- (DONE) Bug 1072 - implement fcvt/fmv instructions in ISACaller (ls006) - 3000
25 | |- Unallocated 5000EUR
27 |-| (IN PROGRESS) Bug 1027 - implement "necessary" additions to SVP64 and Scalar Power ISA - 24000
28 | |- (CONFIRMED, NOT STARTED) Bug 852 - implement grevlut* - 2000
29 | |- (DONE) Bug 972 - addme/subfme carry/overflow is incorrect - 1000
30 | |- (DONE) Bug 1028 - implement integer-versions of fft/dct "butterfly" instructions in ISACaller Simulator - 4000
31 | |- (DONE) Bug 1030 - Enable compilation of PyPowersim on non-power platforms. - 2000
32 | |- (CONFIRMED, NOT STARTED) Bug 1031 - implement CRweird instructions in ISACaller - 3000
33 | |- (CONFIRMED, NOT STARTED) Bug 1034 - implement crternlogi crbinlut and binlut in ISACaller - 3000
34 | |- (IN PROGRESS) Bug 1047 - SVP64 LD/ST Data-Dependent Fail-First providing linked-list walking - 3000
35 | |- (IN PROGRESS) Bug 1061 - change extsb/h/w definitions to scale input size with XLEN rather than convert from fixed sizes - 1000
36 | |- (DONE) Bug 1064 - Change XLEN-ification - 1000
37 | |- (CONFIRMED, IN PROGRESS) Bug 1071 - add parallel prefix sum remap mode - 2000
38 | |- (CONFIRMED, IN PROGRESS) Bug 1116 - evaluate, spec, and implement Vector-Immediates in SVP64 Normal - 2000
40 |-- (CONFIRMED, NOT STARTED) Bug 1032 - Implementation of SVP64 features: elwidth overrides and REMAP - 8000
42 |-- (CONFIRMED, NOT STARTED) Bug 1033 - Implementation and enhancement of "Test API" - 2500
44 |-| (IN PROGRESS) Bug 1035 - Implement Scalar Power ISA v3.1 (32-bit-only) instructions (no PO1) in ISACaller - 7000
45 | |- (DONE) Bug 1120 - Add all scalar 32-bit v3.1 insns to ISACaller - 2000
46 | |- (CONFIRMED, NOT STARTED) Bug 1147 - support Scalar Power ISA v3.1 (32-bit-only) instructions (no PO1) in binutils - 1000
48 |-| (CONFIRMED, NOT STARTED) Bug 1037 - improvements of Libre-SOC core support on FPGA boards - 6000
49 | |- (CONFIRMED, IN PROGRESS) Bug 990 - gram needs changes to work on the orangecrab - 4500
50 | |- (CONFIRMED, IN PROGRESS) Bug 1004 - FPGA bring up for platform definitions - 1500
52 |-- (IN PROGRESS) Bug 1039 - add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core - 3000
54 |-- (CONFIRMED, NOT STARTED) Bug 1150 - implement PO9 changeover and associated tasks - 8000
57 # Meeting 30th aug 2023 16:00 UTC
59 * Checked TOML fields and participants in bugs: 961, 1035, 1068, 1083, 1119, 1120, 1123,
62 **TODO**: Check unallocated budget for bugs 737, 1035, 1026. Also check bug 1047 budget
65 # Meeting 30th aug 2023 08:45 UTC
67 * Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
68 1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132
70 * If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
73 * Jacob please update the json file.
75 * Luke (once checked with Dmitry and Jacob) please do a final check and submit.
77 **TODO**: Dmitry would like to make budget adjustments to
78 [bug #1068](https://bugs.libre-soc.org/show_bug.cgi?id=1068),
79 a subtask of [bug #1003](https://bugs.libre-soc.org/show_bug.cgi?id=1003).
81 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-30.log.html#t2023-08-30T11:18:53)
83 * A meeting later today will be arranged to make adjustments to the budget.
87 * [Bug #1116](https://bugs.libre-soc.org/show_bug.cgi?id=1116#c7) only needs one person to do the work, so budget allocation adjusted accordingly.
89 * Need a discussion on [bug #1047](https://bugs.libre-soc.org/show_bug.cgi?id=1047#c10), as it also intended to done by one person.
91 * Jacob mentioned to re-adjust
92 [bug #1123](https://bugs.libre-soc.org/show_bug.cgi?id=1123#c3) budget to about
93 half of bug #1120. Also Dmitry is not involved in this task (his work will be on a subtask
96 # questions 17 aug 2023
98 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
100 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
104 * There is no overlap, as #976 tackled a different issue (and was already complete
106 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
107 * Bug #1003 does however build on the work from #972.
108 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
110 **TODO: just put clear message describing task. No "Edit: this etc etc"**
112 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
114 **TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
115 3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary. we already know it's an umbrella task, as it has child
116 subtasks. 5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
118 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
122 * Build means that Sadoon provides documentation for setting up a SFFS port
123 of Gentoo and Debian.
124 * Stage 3 tar archive file for Gentoo is now available,
125 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
126 * Debian scripts are still being worked on as of 23rd Aug.
127 * All files required are hosted either on Libre-SOC's ftp or git.
128 * Patching qemu has been discovered to be out-of-scope for this task
129 (far too much work). Sadoon will be creating (or adding sesction to
130 Gentoo/Debian pages) a wiki page describing the
131 work he went through with qemu.
133 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
135 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
137 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
141 * Jacob is still working on figuring out the subtasks which should be focused
142 on for the scope of the On-Going grant.
144 **NOT NEEDED at this stage, can be submitted later. we need to MOVE and get the MoU signed**
146 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
148 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
150 **please REMOVE that. it is NOT necessary to make such a statement.
151 it is already known**
155 * Jacob mentioned there are two major parts
157 1. Decoder/fetch pipeline
160 Cesar likely do the former, Jacob could do the latter.
162 **CORRECTION: JACOB to do both.**
164 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).
168 * Create the framework for testing (or choose existing)
169 (jacob: important clarification -- afaict this task is adding new `StateRunner`
170 and `State` subclasses for FPGA/verilator/etc.
171 This task is *not* for creating a new framework or choosing an existing framework,
172 we already have one with implementations for pypowersim, nmigen simulation of the
173 libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
174 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
175 * Cavatools out of scope.
176 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
177 * Initially pypowersim tested against qemu, then FPGA.
178 * For Simple-V/SVP64 only pypowersim implementation right now.
179 SoC HDL has small subset of SVP64.
182 ### Automated method for removing non-MOU things
184 * Jacob added a feature to automatically remove non-MOU strings.
186 **(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
188 # questions 05 oct 2022
190 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
191 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
194 Again there should be a breakdown of the main tasks, and the associated effort.
195 And a clarification what rates you used.
196 (I'm assuming these are the same, but I've learned not to assume...)
199 yes EUR 3,000 / mo as a yardstick works out ok in practice.
201 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
202 group backed by Intel!)
204 * 2-3 months: Dynamic Partitioned SIMD for nmigen
205 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
206 of FP Rounding Modes and Power ISA Flags
207 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
208 * 3-4 months: Addition of the IEEE754 FPU to the Core
209 * 3-4 months: Addition of other ALUs and pipelines
210 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
211 need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
212 * 3-4 months: Running under Verilator and on FPGAs (big ones)
213 * 4-5 months: Continued documentation, attendance of Conferences online
214 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
215 * 2-3 months plus hosting costs: Establishment and management of CI
216 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
218 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
219 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
220 tasks removing, to fit. we cannot risk committing to tasks at too low a
221 rate to be able to attract interest and committment.
223 Again however I do not have a problem with reducing the scope of this one
224 to only EUR 50,000 to cover some of the less ambitious tasks, with the
225 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
226 priority then a second Grant following up to continue.
229 What would be the concrete (high level) outcome of that project -
230 where would the grant get us? Would there be a new test chip made
231 during the lifespan of the project?
234 Answering on the ASIC first: it is a little early to tell. Coriolis2 needs Timing
235 based Routing completed in order to tackle lower geometries (even 90nm),
236 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
238 is far too small an allocation (12 mm^2 when we need around 100), we
239 really need sky90 which as i understand is still being negotiated and set up.
241 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
242 as a "learning exercise" the 2019-10-029 project was perfect.
243 However as far as "value for money" is concerned, a repeat is honestly
244 less valuable. That said: when it is ready, RED Semiconductor
245 *will* be picking up the Libre-SOC core and taking it to Silicon
246 (28 nm or below). For this Grant Proposal, powerful FPGAs will
249 The concrete outcomes:
251 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
252 Abstraction of its core Language Features. Opportunities then open up
253 to perform strict type checking, length checking, other types of Arithmetic
254 (Complex numbers, Galois Field) and other "filters" as
255 3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
256 2019-02-012 would be the first big showcase.
257 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
258 Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
259 and something worth aiming for.
261 other Libre Formal Proof is Academically developed
262 for an older version of IEEE754: we will
263 target 2008 and 2019 semantics.
264 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
265 present it is Simulations only and the cavatools Cycle-accurate Simulator
266 (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
267 no Virtual Memory, for a start). SMP Support in particular would be strategically
268 very valuable to have, it greatly expands the commercial viability.
269 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
270 an IBM POWER9 Server which lends us credibility but it needs to be put to
273 In other words, mostly "low-level strategic outcomes" on the way to success :)