nlnet_2022_ongoing/discussion.mdwn

   1 # Meeting 30th aug 2023 16:00 UTC
   2
   3 * Checked TOML fields and participants in bugs: 961, 1035, 1068, 1083, 1119, 1120, 1123,
   4 1146, 1147, 1148
   5
   6 # Meeting 30th aug 2023 08:45 UTC
   7
   8 * Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
   9 1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132
  10
  11 * If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
  12 see any problems).
  13
  14 * Jacob please update the json file.
  15
  16 * Luke (once checked with Dmitry and Jacob) please do a final check and submit.
  17
  18 **TODO**: Dmitry would like to make budget adjustments to
  19 [bug #1068](https://bugs.libre-soc.org/show_bug.cgi?id=1068),
  20 a subtask of [bug #1003](https://bugs.libre-soc.org/show_bug.cgi?id=1003).
  21 See the
  22 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-30.log.html#t2023-08-30T11:18:53)
  23
  24 * A meeting later today will be arranged to make adjustments to the budget.
  25
  26 Edit:
  27
  28 * [Bug #1116](https://bugs.libre-soc.org/show_bug.cgi?id=1116#c7) only needs one person to do the work, so budget allocation adjusted accordingly.
  29
  30 * Need a discussion on [bug #1047](https://bugs.libre-soc.org/show_bug.cgi?id=1047#c10), as it also intended to done by one person.
  31
  32 * Jacob mentioned to re-adjust
  33 [bug #1123](https://bugs.libre-soc.org/show_bug.cgi?id=1123#c3) budget to about
  34 half of bug #1120. Also Dmitry is not involved in this task (his work will be on a subtask
  35 bug #1035).
  36
  37 # questions 17 aug 2023
  38
  39 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
  40
  41 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
  42
  43 ### Bug #1003
  44
  45 * There is no overlap, as #976 tackled a different issue (and was already complete
  46 before #1003).
  47 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  48 * Bug #1003 does however build on the work from #972.
  49 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  50
  51 **TODO: just put clear message describing task.  No "Edit: this etc etc"**
  52
  53 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  54
  55 **TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
  56  3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary.  we already know it's an umbrella task, as it has child
  57 subtasks.  5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
  58
  59 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  60
  61 ### Bug #999
  62
  63 * Build means that Sadoon provides documentation for setting up a SFFS port
  64 of Gentoo and Debian.
  65 * Stage 3 tar archive file for Gentoo is now available,
  66 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  67 * Debian scripts are still being worked on as of 23rd Aug.
  68 * All files required are hosted either on Libre-SOC's ftp or git.
  69 * Patching qemu has been discovered to be out-of-scope for this task
  70 (far too much work). Sadoon will be creating (or adding sesction to
  71 Gentoo/Debian pages) a wiki page describing the
  72 work he went through with qemu.
  73
  74 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
  75
  76 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
  77
  78 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
  79
  80 ### Bugs 1025/1026
  81
  82 * Jacob is still working on figuring out the subtasks which should be focused
  83 on for the scope of the On-Going grant.
  84
  85 **NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**
  86
  87 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
  88 the MoU. See
  89 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
  90
  91 **please REMOVE that.  it is NOT necessary to make such a statement.
  92 it is already known**
  93
  94 ### Bug 1032
  95
  96 * Jacob mentioned there are two major parts
  97
  98 1. Decoder/fetch pipeline
  99 2. Execution unit
 100
 101 Cesar likely do the former, Jacob could do the latter.
 102
 103 **CORRECTION: JACOB to do both.**
 104
 105 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).
 106
 107 ### Bug 1033
 108
 109 * Create the framework for testing (or choose existing)
 110   (jacob: important clarification -- afaict this task is adding new `StateRunner`
 111   and `State` subclasses for FPGA/verilator/etc.
 112   This task is *not* for creating a new framework or choosing an existing framework,
 113   we already have one with implementations for pypowersim, nmigen simulation of the
 114   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
 115 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
 116 * Cavatools out of scope.
 117 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
 118 * Initially pypowersim tested against qemu, then FPGA.
 119 * For Simple-V/SVP64 only pypowersim implementation right now.
 120 SoC HDL has small subset of SVP64.
 121
 122
 123 ### Automated method for removing non-MOU things
 124
 125 * Jacob added a feature to automatically remove non-MOU strings.
 126
 127 **(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
 128
 129 # questions 05 oct 2022
 130
 131 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
 132 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
 133
 134 **
 135     Again there should be a breakdown of the main tasks, and the associated effort.
 136     And a clarification what rates you used.
 137     (I'm assuming these are the same, but I've learned not to assume...)
 138 **
 139
 140 yes EUR 3,000 / mo as a yardstick works out ok in practice.
 141
 142 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
 143 group backed by Intel!)
 144
 145 * 2-3 months: Dynamic Partitioned SIMD for nmigen
 146 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
 147   of FP Rounding Modes and Power ISA Flags
 148 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 149 * 3-4 months: Addition of the IEEE754 FPU to the Core
 150 * 3-4 months: Addition of other ALUs and pipelines
 151 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
 152   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 153 * 3-4 months: Running under Verilator and on FPGAs (big ones)
 154 * 4-5 months: Continued documentation, attendance of Conferences online
 155 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
 156 * 2-3 months plus hosting costs: Establishment and management of CI
 157 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
 158
 159 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
 160 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 161 tasks removing, to fit. we cannot risk committing to tasks at too low a
 162 rate to be able to attract interest and committment.
 163
 164 Again however I do not have a problem with reducing the scope of this one
 165 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 166 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 167 priority then a second Grant following up to continue.
 168
 169 **
 170     What would be the concrete (high level) outcome of that project -
 171     where would the grant get us? Would there be a new test chip made
 172     during the lifespan of the project?
 173 **
 174
 175 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 176 based Routing completed in order to tackle lower geometries (even 90nm),
 177 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 178 sky130
 179 is far too small an allocation (12 mm^2 when we need around 100), we
 180 really need sky90 which as i understand is still being negotiated and set up.
 181
 182 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 183 as a "learning exercise" the 2019-10-029 project was perfect.
 184 However as far as "value for money" is concerned, a repeat is honestly
 185 less valuable.  That said: when it is ready, RED Semiconductor
 186 *will* be picking up the Libre-SOC core and taking it to Silicon
 187 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 188 get us a long way.
 189
 190 The concrete outcomes:
 191
 192 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 193   Abstraction of its core Language Features.  Opportunities then open up
 194   to perform strict type checking, length checking, other types of Arithmetic
 195   (Complex numbers, Galois Field) and other "filters" as
 196   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 197   2019-02-012 would be the first big showcase.
 198 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 199   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 200   and something worth aiming for.
 201   The only
 202   other Libre Formal Proof is Academically developed
 203   for an older version of IEEE754: we will
 204   target 2008 and 2019 semantics.
 205 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 206   present it is Simulations only and the cavatools Cycle-accurate Simulator
 207   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 208   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 209   very valuable to have, it greatly expands the commercial viability.
 210 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 211   an IBM POWER9 Server which lends us credibility but it needs to be put to
 212   good use!
 213
 214 In other words, mostly "low-level strategic outcomes" on the way to success :)