nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 ### Bug #1003
   8
   9 * There is no overlap, as #976 tackled a different issue (and was already complete
  10 before #1003).
  11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  12 * Bug #1003 does however build on the work from #972.
  13
  14 ### Bug #999
  15
  16 * Build means that Sadoon provides documentation for setting up a SFFS port
  17 of Gentoo and Debian.
  18 * Stage 3 tar archive file for Gentoo is now available,
  19 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  20 * Debian scripts are still being worked on as of 23rd Aug.
  21 * All files required are hosted either on Libre-SOC's ftp or git.
  22 * Patching qemu has been discovered to be out-of-scope for this task
  23 (far too much work), and Sadoon will be creating a wiki page.
  24
  25 ### Bugs 1025/1026
  26
  27 * Jacob is still working on figuring out the subtasks which should be focused
  28 on for the scope of the On-Going grant.
  29
  30 # questions 05 oct 2022
  31
  32 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  33 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  34
  35 **
  36     Again there should be a breakdown of the main tasks, and the associated effort.
  37     And a clarification what rates you used.
  38     (I'm assuming these are the same, but I've learned not to assume...)
  39 **
  40
  41 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  42
  43 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  44 group backed by Intel!)
  45
  46 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  47 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  48   of FP Rounding Modes and Power ISA Flags
  49 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
  50 * 3-4 months: Addition of the IEEE754 FPU to the Core
  51 * 3-4 months: Addition of other ALUs and pipelines
  52 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  53   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
  54 * 3-4 months: Running under Verilator and on FPGAs (big ones)
  55 * 4-5 months: Continued documentation, attendance of Conferences online
  56 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
  57 * 2-3 months plus hosting costs: Establishment and management of CI
  58 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
  59
  60 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
  61 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
  62 tasks removing, to fit. we cannot risk committing to tasks at too low a
  63 rate to be able to attract interest and committment.
  64
  65 Again however I do not have a problem with reducing the scope of this one
  66 to only EUR 50,000 to cover some of the less ambitious tasks, with the
  67 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
  68 priority then a second Grant following up to continue.
  69
  70 **
  71     What would be the concrete (high level) outcome of that project -
  72     where would the grant get us? Would there be a new test chip made
  73     during the lifespan of the project?
  74 **
  75
  76 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
  77 based Routing completed in order to tackle lower geometries (even 90nm),
  78 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
  79 sky130
  80 is far too small an allocation (12 mm^2 when we need around 100), we
  81 really need sky90 which as i understand is still being negotiated and set up.
  82
  83 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
  84 as a "learning exercise" the 2019-10-029 project was perfect.
  85 However as far as "value for money" is concerned, a repeat is honestly
  86 less valuable.  That said: when it is ready, RED Semiconductor
  87 *will* be picking up the Libre-SOC core and taking it to Silicon
  88 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
  89 get us a long way.
  90
  91 The concrete outcomes:
  92
  93 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
  94   Abstraction of its core Language Features.  Opportunities then open up
  95   to perform strict type checking, length checking, other types of Arithmetic
  96   (Complex numbers, Galois Field) and other "filters" as
  97   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
  98   2019-02-012 would be the first big showcase.
  99 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 100   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 101   and something worth aiming for.
 102   The only
 103   other Libre Formal Proof is Academically developed
 104   for an older version of IEEE754: we will
 105   target 2008 and 2019 semantics.
 106 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 107   present it is Simulations only and the cavatools Cycle-accurate Simulator
 108   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 109   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 110   very valuable to have, it greatly expands the commercial viability.
 111 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 112   an IBM POWER9 Server which lends us credibility but it needs to be put to
 113   good use!
 114
 115 In other words, mostly "low-level strategic outcomes" on the way to success :)