nlnet_2022_ongoing/discussion.mdwn

   1 # Meeting 30th aug 2023 08:45 UTC
   2
   3 * Updated the TOML fields for the following bugs: 737, 852, 990, 999, 1004, 1024, 1025,
   4 1026, 1031, 1032, 1033, 1034, 1035, 1039, 1086, 1116, 1120, 1123, 1128, 1130, 1131, 1132
   5
   6 * If Dmitriy has any more ammendments to make, please check your subtasks (we didn't
   7 see any problems).
   8
   9 * Jacob please update the json file.
  10
  11 * Luke (once checked with Dmitry and Jacob) please do a final check and submit.
  12
  13 **TODO**: Dmitry would like to make budget adjustments to
  14 [bug #1068](https://bugs.libre-soc.org/show_bug.cgi?id=1068),
  15 a subtask of [bug #1003](https://bugs.libre-soc.org/show_bug.cgi?id=1003).
  16 See the
  17 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-30.log.html#t2023-08-30T11:18:53)
  18
  19 * A meeting later today will be arranged to make adjustments to the budget.
  20
  21 Edit:
  22
  23 * [Bug #1116](https://bugs.libre-soc.org/show_bug.cgi?id=1116#c7) only needs one person to do the work, so budget allocation adjusted accordingly.
  24
  25 * Need a discussion on [bug #1047](https://bugs.libre-soc.org/show_bug.cgi?id=1047#c10), as it also intended to done by one person.
  26
  27 * Jacob mentioned to re-adjust
  28 [bug #1123](https://bugs.libre-soc.org/show_bug.cgi?id=1123#c3) budget to about
  29 half of bug #1120. Also Dmitry is not involved in this task (his work will be on a subtask
  30 bug #1035).
  31
  32 # questions 17 aug 2023
  33
  34 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
  35
  36 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
  37
  38 ### Bug #1003
  39
  40 * There is no overlap, as #976 tackled a different issue (and was already complete
  41 before #1003).
  42 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  43 * Bug #1003 does however build on the work from #972.
  44 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  45
  46 **TODO: just put clear message describing task.  No "Edit: this etc etc"**
  47
  48 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  49
  50 **TODO: 1) the 1st sentence does not mention binutils. 2. it needs to say "continuation of bug #976"
  51  3. a "--" is needed. 4. the paragraph "this is an umbrella task" is unnecessary.  we already know it's an umbrella task, as it has child
  52 subtasks.  5. the last sentence which repeats for the *third* or fourth time "this is a task" can be removed. 6. again "bug #976" not "#976".**
  53
  54 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1003#c0).
  55
  56 ### Bug #999
  57
  58 * Build means that Sadoon provides documentation for setting up a SFFS port
  59 of Gentoo and Debian.
  60 * Stage 3 tar archive file for Gentoo is now available,
  61 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  62 * Debian scripts are still being worked on as of 23rd Aug.
  63 * All files required are hosted either on Libre-SOC's ftp or git.
  64 * Patching qemu has been discovered to be out-of-scope for this task
  65 (far too much work). Sadoon will be creating (or adding sesction to
  66 Gentoo/Debian pages) a wiki page describing the
  67 work he went through with qemu.
  68
  69 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
  70
  71 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
  72
  73 * Edit: Sadoon updated comments 0 for bugs #999, 1130, 1131, 1132.
  74
  75 ### Bugs 1025/1026
  76
  77 * Jacob is still working on figuring out the subtasks which should be focused
  78 on for the scope of the On-Going grant.
  79
  80 **NOT NEEDED at this stage, can be submitted later.  we need to MOVE and get the MoU signed**
  81
  82 Edit: Jacob specified that 1025/1026 subtasks are not going to be part of
  83 the MoU. See
  84 [IRC log](https://libre-soc.org/irclog/%23libre-soc.2023-08-24.log.html#t2023-08-24T17:27:20)
  85
  86 **please REMOVE that.  it is NOT necessary to make such a statement.
  87 it is already known**
  88
  89 ### Bug 1032
  90
  91 * Jacob mentioned there are two major parts
  92
  93 1. Decoder/fetch pipeline
  94 2. Execution unit
  95
  96 Cesar likely do the former, Jacob could do the latter.
  97
  98 **CORRECTION: JACOB to do both.**
  99
 100 * Edit: Please see updated [comment 0](https://bugs.libre-soc.org/show_bug.cgi?id=1032#c0).
 101
 102 ### Bug 1033
 103
 104 * Create the framework for testing (or choose existing)
 105   (jacob: important clarification -- afaict this task is adding new `StateRunner`
 106   and `State` subclasses for FPGA/verilator/etc.
 107   This task is *not* for creating a new framework or choosing an existing framework,
 108   we already have one with implementations for pypowersim, nmigen simulation of the
 109   libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
 110 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
 111 * Cavatools out of scope.
 112 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
 113 * Initially pypowersim tested against qemu, then FPGA.
 114 * For Simple-V/SVP64 only pypowersim implementation right now.
 115 SoC HDL has small subset of SVP64.
 116
 117
 118 ### Automated method for removing non-MOU things
 119
 120 * Jacob added a feature to automatically remove non-MOU strings.
 121
 122 **(and didn't follow instructions which was to only add support for "--...--" the standard line-break of markdown). now additional work has to be done looking for the extremely irritating and tiresome and completely undocumented "trigger-sentence" which if typed incorrectly will not do its job)**
 123
 124 # questions 05 oct 2022
 125
 126 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
 127 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
 128
 129 **
 130     Again there should be a breakdown of the main tasks, and the associated effort.
 131     And a clarification what rates you used.
 132     (I'm assuming these are the same, but I've learned not to assume...)
 133 **
 134
 135 yes EUR 3,000 / mo as a yardstick works out ok in practice.
 136
 137 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
 138 group backed by Intel!)
 139
 140 * 2-3 months: Dynamic Partitioned SIMD for nmigen
 141 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
 142   of FP Rounding Modes and Power ISA Flags
 143 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
 144 * 3-4 months: Addition of the IEEE754 FPU to the Core
 145 * 3-4 months: Addition of other ALUs and pipelines
 146 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
 147   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
 148 * 3-4 months: Running under Verilator and on FPGAs (big ones)
 149 * 4-5 months: Continued documentation, attendance of Conferences online
 150 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
 151 * 2-3 months plus hosting costs: Establishment and management of CI
 152 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
 153
 154 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
 155 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
 156 tasks removing, to fit. we cannot risk committing to tasks at too low a
 157 rate to be able to attract interest and committment.
 158
 159 Again however I do not have a problem with reducing the scope of this one
 160 to only EUR 50,000 to cover some of the less ambitious tasks, with the
 161 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
 162 priority then a second Grant following up to continue.
 163
 164 **
 165     What would be the concrete (high level) outcome of that project -
 166     where would the grant get us? Would there be a new test chip made
 167     during the lifespan of the project?
 168 **
 169
 170 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 171 based Routing completed in order to tackle lower geometries (even 90nm),
 172 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 173 sky130
 174 is far too small an allocation (12 mm^2 when we need around 100), we
 175 really need sky90 which as i understand is still being negotiated and set up.
 176
 177 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 178 as a "learning exercise" the 2019-10-029 project was perfect.
 179 However as far as "value for money" is concerned, a repeat is honestly
 180 less valuable.  That said: when it is ready, RED Semiconductor
 181 *will* be picking up the Libre-SOC core and taking it to Silicon
 182 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 183 get us a long way.
 184
 185 The concrete outcomes:
 186
 187 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 188   Abstraction of its core Language Features.  Opportunities then open up
 189   to perform strict type checking, length checking, other types of Arithmetic
 190   (Complex numbers, Galois Field) and other "filters" as
 191   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 192   2019-02-012 would be the first big showcase.
 193 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 194   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 195   and something worth aiming for.
 196   The only
 197   other Libre Formal Proof is Academically developed
 198   for an older version of IEEE754: we will
 199   target 2008 and 2019 semantics.
 200 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 201   present it is Simulations only and the cavatools Cycle-accurate Simulator
 202   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 203   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 204   very valuable to have, it greatly expands the commercial viability.
 205 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 206   an IBM POWER9 Server which lends us credibility but it needs to be put to
 207   good use!
 208
 209 In other words, mostly "low-level strategic outcomes" on the way to success :)