nlnet_2022_ongoing/discussion.mdwn

   1 # questions 17 aug 2023
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
   4
   5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
   6
   7 ### Bug #1003
   8
   9 * There is no overlap, as #976 tackled a different issue (and was already complete
  10 before #1003).
  11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
  12 * Bug #1003 does however build on the work from #972.
  13 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
  14
  15 ### Bug #999
  16
  17 * Build means that Sadoon provides documentation for setting up a SFFS port
  18 of Gentoo and Debian.
  19 * Stage 3 tar archive file for Gentoo is now available,
  20 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
  21 * Debian scripts are still being worked on as of 23rd Aug.
  22 * All files required are hosted either on Libre-SOC's ftp or git.
  23 * Patching qemu has been discovered to be out-of-scope for this task
  24 (far too much work). Sadoon will be creating (or adding sesction to
  25 Gentoo/Debian pages) a wiki page describing the
  26 work he went through with qemu.
  27
  28 ### Bugs 1025/1026
  29
  30 * Jacob is still working on figuring out the subtasks which should be focused
  31 on for the scope of the On-Going grant.
  32
  33 ### Bug 1032
  34
  35 * Jacob mentioned there are two major parts
  36
  37 1. Decoder/fetch pipeline
  38 2. Execution unit
  39
  40 Cesar likely do the former, Jacob could do the latter.
  41
  42 ### Bug 1033
  43
  44 * Create the framework for testing (or choose existing)
  45 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
  46 * Cavatools out of scope.
  47 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
  48 * Initially pypowersim tested against qemu, then FPGA.
  49 * For Simple-V/SVP64 only pypowersim implementation right now.
  50 SoC HDL has small subset of SVP64.
  51
  52
  53 ### Automated method for removing non-MOU things
  54
  55 * Jacob added a feature to automatically remove non-MOU strings.
  56
  57
  58 # questions 05 oct 2022
  59
  60 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
  61 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
  62
  63 **
  64     Again there should be a breakdown of the main tasks, and the associated effort.
  65     And a clarification what rates you used.
  66     (I'm assuming these are the same, but I've learned not to assume...)
  67 **
  68
  69 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  70
  71 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  72 group backed by Intel!)
  73
  74 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  75 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
  76   of FP Rounding Modes and Power ISA Flags
  77 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
  78 * 3-4 months: Addition of the IEEE754 FPU to the Core
  79 * 3-4 months: Addition of other ALUs and pipelines
  80 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  81   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
  82 * 3-4 months: Running under Verilator and on FPGAs (big ones)
  83 * 4-5 months: Continued documentation, attendance of Conferences online
  84 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
  85 * 2-3 months plus hosting costs: Establishment and management of CI
  86 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
  87
  88 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
  89 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
  90 tasks removing, to fit. we cannot risk committing to tasks at too low a
  91 rate to be able to attract interest and committment.
  92
  93 Again however I do not have a problem with reducing the scope of this one
  94 to only EUR 50,000 to cover some of the less ambitious tasks, with the
  95 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
  96 priority then a second Grant following up to continue.
  97
  98 **
  99     What would be the concrete (high level) outcome of that project -
 100     where would the grant get us? Would there be a new test chip made
 101     during the lifespan of the project?
 102 **
 103
 104 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 105 based Routing completed in order to tackle lower geometries (even 90nm),
 106 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
 107 sky130
 108 is far too small an allocation (12 mm^2 when we need around 100), we
 109 really need sky90 which as i understand is still being negotiated and set up.
 110
 111 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
 112 as a "learning exercise" the 2019-10-029 project was perfect.
 113 However as far as "value for money" is concerned, a repeat is honestly
 114 less valuable.  That said: when it is ready, RED Semiconductor
 115 *will* be picking up the Libre-SOC core and taking it to Silicon
 116 (28 nm or below).  For this Grant Proposal, powerful FPGAs will
 117 get us a long way.
 118
 119 The concrete outcomes:
 120
 121 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
 122   Abstraction of its core Language Features.  Opportunities then open up
 123   to perform strict type checking, length checking, other types of Arithmetic
 124   (Complex numbers, Galois Field) and other "filters" as
 125   3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
 126   2019-02-012 would be the first big showcase.
 127 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
 128   Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
 129   and something worth aiming for.
 130   The only
 131   other Libre Formal Proof is Academically developed
 132   for an older version of IEEE754: we will
 133   target 2008 and 2019 semantics.
 134 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
 135   present it is Simulations only and the cavatools Cycle-accurate Simulator
 136   (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
 137   no Virtual Memory, for a start).  SMP Support in particular would be strategically
 138   very valuable to have, it greatly expands the commercial viability.
 139 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
 140   an IBM POWER9 Server which lends us credibility but it needs to be put to
 141   good use!
 142
 143 In other words, mostly "low-level strategic outcomes" on the way to success :)