nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 * 2022-08-107
   4 * [[nlnet_2022_ongoing/discussion]]
   5
   6 ## Project name
   7
   8 Libre-SOC Ongoing 2022/3
   9
  10 ## Website / wiki
  11
  12 <https://libre-soc.org/nlnet_2022_ongoing>
  13
  14 # Summary
  15
  16 The funding to date from NLnet via EU Grants has been amazing and resulted
  17 in significant development of Digitally-Sovereign VLSI designs.
  18 Continuing to further that initial research to create High Performance
  19 Compute for ultimate use in end-user products such as smartphones desktops
  20 laptops and Industrial Embedded PCs is clearly important.
  21 We therefore aim to further the IEEE754 Pipelines, associated Formal
  22 Correctness Proofs, and continue implementing unit tests, Simulator,
  23 Processor Core implementing Power ISA and Draft SVP64, as well as
  24 documentation and attending conferences.
  25
  26 # Submitted to NLnet
  27
  28 Please be short and to the point in your answers; focus primarily on
  29 the what and how, not so much on the why. Add longer descriptions as
  30 attachments (see below). If English isn't your first language, don't
  31 worry - our reviewers don't care about spelling errors, only about
  32 great ideas. We apologise for the inconvenience of having to submit in
  33 English. On the up side, you can be as technical as you need to be (but
  34 you don't have to). Do stay concrete. Use plain text in your reply only,
  35 if you need any HTML to make your point please include this as attachment.
  36
  37 ## Abstract: Can you explain the whole project and its expected outcome(s).
  38
  39 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  40 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  41 of submitting the required Scalable Vector Extension to the OpenPOWER
  42 Foundation: this Grant Request focusses more on continuing to
  43 *implement* that Scalable Vector Extension.
  44
  45 With the entire project being 100% FOSSHW and managed strictly as a
  46 Libre Project under strict Full Transparency conditions the end result
  47 is a High-performance Processor Initiative that EU Citizens can trust.
  48
  49 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  50
  51 As mentioned in 2022-08-51,
  52 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  53 and includes
  54
  55 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  56 * the world's first in-place Discrete Cosine Transform algorithm;
  57 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  58  to do an 800,000 transistor fully automated RTL2GDSII
  59 tape-out;
  60 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  61   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  62 * development of an Interoperability "Test API" for Power ISA systems,
  63   with thousands of unit tests.
  64
  65 and much more. The side-benefits alone for EU citizens are enormous.
  66
  67 # Requested Amount
  68
  69 EUR 100,000.
  70
  71 # Explain what the requested budget will be used for?
  72
  73 (Note having completed 2022-02-012 we meet the conditions for a
  74 larger budget request)
  75
  76 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  77 and satisfying Voting Members of its suitability, we need to proceed
  78 with implementing SVP64 and underlying infrastructure:
  79
  80 * Dynamic Partitioned SIMD for nmigen
  81 * Completion of IEEE754 FP Formal Correctness Proofs
  82 * Completion of an In-Order Single-Issue core implementing SVP64
  83 * Addition of the IEEE754 FPU to the Core
  84 * Addition of other ALUs and pipelines (bitmanip, video)
  85   implementing new Draft instructions from 2022-08-051
  86 * Addition of SMP (multi-core) support
  87 * Running under Verilator and on FPGAs (big ones) which will
  88   need to be investigated, bought, and the Libre-Licensed tools support
  89   potentially added or improved
  90 * Continued documentation, attendance of Conferences online
  91 * Begin investigating Multi-Issue Out-of-Order, continuing
  92   the 6600 Scoreboard research from 2019-02-012
  93 * Establishment and management of Continuous Integration
  94   infrastructure and upgrading the Libre-SOC IT systems
  95   (currently a single 4GB VM)
  96 * If there is sufficient budget we would like to begin investigating
  97   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
  98
  99 several more practical details which help very much to ensure that the
 100 efforts to date, funded very kindly by NLnet, reach fruition as part
 101 of providing EU Citizens with a powerful Libre alternative processor
 102 option.
 103
 104 # Compare your own project with existing or historical efforts.
 105
 106 As hinted at in 2022-08-051
 107 we are basically developing a Cray-style Supercomputer, leveraging
 108 the Supercomputing-class Power ISA
 109 and extending it.  Similar historic ISAs include
 110 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 111 They are all proprietary systems: Libre-SOC's efforts are entirely
 112 FOSSHW.
 113
 114 Whilst the European Processor Initiative is focussing exclusively
 115 on RISC-V, due to the amount of time it takes to assess an ISA's
 116 suitability it has to be said that it is being discovered, very slowly,
 117 that RISC-V is not suited to High-Performance Supercomputing
 118 workloads. The best explanation online is here:
 119 <https://news.ycombinator.com/item?id=24459041>
 120
 121 Therefore this project is a really important alternative
 122 being based on a much more suitable High-performance
 123 base that has the backing of
 124 IBM for over 25 years, and is now an Open ISA.
 125 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 126
 127 ## What are significant technical challenges you expect to solve during the project, if any?
 128
 129 Processor design is HARD. This is dramatically underestimated.  We are
 130 therefore taking a careful and considered incremental approach, using
 131 Software Engineering programming techniques, developing unit tests
 132 at every level and ensuring rigorous documentation and Project coordination
 133 guidelines are adhered to.
 134
 135 We also make significant use of automation,
 136 compiler technology and abstraction
 137 which would never be considered by Hardware-only VLSI Engineers.
 138 By taking a step back we simplify the approach to one that is
 139 manageable by a much smaller team.
 140
 141 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 142
 143 As in 2022-08-051
 144 we are already set to submit presentations through multiple Conferences
 145 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 146 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 147 so is accessible to all.
 148
 149 # Extra info to be submitted
 150