nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 * 2022-08-107
   4 * [[nlnet_2022_ongoing/discussion]]
   5
   6 ## Project name
   7
   8 Libre-SOC Ongoing 2022/3
   9
  10 ## Website / wiki
  11
  12 <https://libre-soc.org/nlnet_2022_ongoing>
  13
  14 Please be short and to the point in your answers; focus primarily on
  15 the what and how, not so much on the why. Add longer descriptions as
  16 attachments (see below). If English isn't your first language, don't
  17 worry - our reviewers don't care about spelling errors, only about
  18 great ideas. We apologise for the inconvenience of having to submit in
  19 English. On the up side, you can be as technical as you need to be (but
  20 you don't have to). Do stay concrete. Use plain text in your reply only,
  21 if you need any HTML to make your point please include this as attachment.
  22
  23 ## Abstract: Can you explain the whole project and its expected outcome(s).
  24
  25 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  26 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  27 of submitting the required Scalable Vector Extension to the OpenPOWER
  28 Foundation: this Grant Request focusses more on continuing to
  29 *implement* that Scalable Vector Extension.
  30
  31 With the entire project being 100% FOSSHW and managed strictly as a
  32 Libre Project under strict Full Transparency conditions the end result
  33 is a High-performance Processor Initiative that EU Citizens can trust.
  34
  35 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  36
  37 As mentioned in 2022-08-51,
  38 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  39 and includes
  40
  41 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  42 * the world's first in-place Discrete Cosine Transform algorithm;
  43 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  44  to do an 800,000 transistor fully automated RTL2GDSII
  45 tape-out;
  46 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  47   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  48 * development of an Interoperability "Test API" for Power ISA systems,
  49   with thousands of unit tests.
  50
  51 and much more. The side-benefits alone for EU citizens are enormous.
  52
  53 # Requested Amount
  54
  55 EUR 100,000.
  56
  57 # Explain what the requested budget will be used for?
  58
  59 (Note having completed 2022-02-012 we meet the conditions for a
  60 larger budget request)
  61
  62 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  63 and satisfying Voting Members of its suitability, we need to proceed
  64 with implementing SVP64 and underlying infrastructure:
  65
  66 * Dynamic Partitioned SIMD for nmigen
  67 * Completion of IEEE754 FP Formal Correctness Proofs
  68 * Completion of an In-Order Single-Issue core implementing SVP64
  69 * Addition of the IEEE754 FPU to the Core
  70 * Addition of other ALUs and pipelines (bitmanip, video)
  71   implementing new Draft instructions from 2022-08-051
  72 * Addition of SMP (multi-core) support
  73 * Running under Verilator and on FPGAs (big ones) which will
  74   need to be investigated, bought, and the Libre-Licensed tools support
  75   potentially added or improved
  76 * Continued documentation, attendance of Conferences online
  77 * Begin investigating Multi-Issue Out-of-Order, continuing
  78   the 6600 Scoreboard research from 2019-02-012
  79 * Establishment and management of Continuous Integration
  80   infrastructure and upgrading the Libre-SOC IT systems
  81   (currently a single 4GB VM)
  82 * If there is sufficient budget we would like to begin investigating
  83   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
  84
  85 several more practical details which help very much to ensure that the
  86 efforts to date, funded very kindly by NLnet, reach fruition as part
  87 of providing EU Citizens with a powerful Libre alternative processor
  88 option.
  89
  90 # Compare your own project with existing or historical efforts.
  91
  92 As hinted at in 2022-08-051
  93 we are basically developing a Cray-style Supercomputer, leveraging
  94 the Supercomputing-class Power ISA
  95 and extending it.  Similar historic ISAs include
  96 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
  97 They are all proprietary systems: Libre-SOC's efforts are entirely
  98 FOSSHW.
  99
 100 Whilst the European Processor Initiative is focussing exclusively
 101 on RISC-V, due to the amount of time it takes to assess an ISA's
 102 suitability it has to be said that it is being discovered, very slowly,
 103 that RISC-V is not suited to High-Performance Supercomputing
 104 workloads. The best explanation online is here:
 105 <https://news.ycombinator.com/item?id=24459041>
 106
 107 Therefore this project is a really important alternative
 108 being based on a much more suitable High-performance
 109 base that has the backing of
 110 IBM for over 25 years, and is now an Open ISA.
 111 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 112
 113 ## What are significant technical challenges you expect to solve during the project, if any?
 114
 115 Processor design is HARD. This is dramatically underestimated.  We are
 116 therefore taking a careful and considered incremental approach, using
 117 Software Engineering programming techniques, developing unit tests
 118 at every level and ensuring rigorous documentation and Project coordination
 119 guidelines are adhered to.
 120
 121 We also make significant use of automation,
 122 compiler technology and abstraction
 123 which would never be considered by Hardware-only VLSI Engineers.
 124 By taking a step back we simplify the approach to one that is
 125 manageable by a much smaller team.
 126
 127 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 128
 129 As in 2022-08-051
 130 we are already set to submit presentations through multiple Conferences
 131 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 132 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 133 so is accessible to all.
 134
 135 # Extra info to be submitted
 136