nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 2022-08-107
   4
   5 ## Project name
   6
   7 Libre-SOC Ongoing 2022/3
   8
   9 ## Website / wiki
  10
  11 <https://libre-soc.org/nlnet_2022_ongoing>
  12
  13 Please be short and to the point in your answers; focus primarily on
  14 the what and how, not so much on the why. Add longer descriptions as
  15 attachments (see below). If English isn't your first language, don't
  16 worry - our reviewers don't care about spelling errors, only about
  17 great ideas. We apologise for the inconvenience of having to submit in
  18 English. On the up side, you can be as technical as you need to be (but
  19 you don't have to). Do stay concrete. Use plain text in your reply only,
  20 if you need any HTML to make your point please include this as attachment.
  21
  22 ## Abstract: Can you explain the whole project and its expected outcome(s).
  23
  24 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  25 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  26 of submitting the required Scalable Vector Extension to the OpenPOWER
  27 Foundation: this Grant Request focusses more on continuing to
  28 *implement* that Scalable Vector Extension.
  29
  30 With the entire project being 100% FOSSHW and managed strictly as a
  31 Libre Project under strict Full Transparency conditions the end result
  32 is a High-performance Processor Initiative that EU Citizens can trust.
  33
  34 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  35
  36 As mentioned in 2022-08-51,
  37 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  38 and includes
  39
  40 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  41 * the world's first in-place Discrete Cosine Transform algorithm;
  42 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  43  to do an 800,000 transistor fully automated RTL2GDSII
  44 tape-out;
  45 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  46   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  47 * development of an Interoperability "Test API" for Power ISA systems,
  48   with thousands of unit tests.
  49
  50 and much more. The side-benefits alone for EU citizens are enormous.
  51
  52 # Requested Amount
  53
  54 EUR 100,000.
  55
  56 # Explain what the requested budget will be used for?
  57
  58 (Note having completed 2022-02-012 we meet the conditions for a
  59 larger budget request)
  60
  61 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  62 and satisfying Voting Members of its suitability, we need to proceed
  63 with implementing SVP64 and underlying infrastructure:
  64
  65 * Dynamic Partitioned SIMD for nmigen
  66 * Completion of IEEE754 FP Formal Correctness Proofs
  67 * Completion of an In-Order Single-Issue core implementing SVP64
  68 * Addition of the IEEE754 FPU to the Core
  69 * Addition of other ALUs and pipelines (bitmanip, video)
  70   implementing new Draft instructions from 2022-08-051
  71 * Addition of SMP (multi-core) support
  72 * Running under Verilator and on FPGAs (big ones) which will
  73   need to be investigated, bought, and the Libre-Licensed tools support
  74   potentially added or improved
  75 * Continued documentation, attendance of Conferences online
  76 * Begin investigating Multi-Issue Out-of-Order, continuing
  77   the 6600 Scoreboard research from 2019-02-012
  78 * Establishment and management of Continuous Integration
  79   infrastructure and upgrading the Libre-SOC IT systems
  80   (currently a single 4GB VM)
  81 * If there is sufficient budget we would like to begin investigating
  82   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
  83
  84 several more practical details which help very much to ensure that the
  85 efforts to date, funded very kindly by NLnet, reach fruition as part
  86 of providing EU Citizens with a powerful Libre alternative processor
  87 option.
  88
  89 # Compare your own project with existing or historical efforts.
  90
  91 As hinted at in 2022-08-051
  92 we are basically developing a Cray-style Supercomputer, leveraging
  93 the Supercomputing-class Power ISA
  94 and extending it.  Similar historic ISAs include
  95 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
  96 They are all proprietary systems: Libre-SOC's efforts are entirely
  97 FOSSHW.
  98
  99 Whilst the European Processor Initiative is focussing exclusively
 100 on RISC-V, due to the amount of time it takes to assess an ISA's
 101 suitability it has to be said that it is being discovered, very slowly,
 102 that RISC-V is not suited to High-Performance Supercomputing
 103 workloads. The best explanation online is here:
 104 <https://news.ycombinator.com/item?id=24459041>
 105
 106 Therefore this project is a really important alternative
 107 being based on a much more suitable High-performance
 108 base that has the backing of
 109 IBM for over 25 years, and is now an Open ISA.
 110 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 111
 112 ## What are significant technical challenges you expect to solve during the project, if any?
 113
 114 Processor design is HARD. This is dramatically underestimated.  We are
 115 therefore taking a careful and considered incremental approach, using
 116 Software Engineering programming techniques, developing unit tests
 117 at every level and ensuring rigorous documentation and Project coordination
 118 guidelines are adhered to.
 119
 120 We also make significant use of automation,
 121 compiler technology and abstraction
 122 which would never be considered by Hardware-only VLSI Engineers.
 123 By taking a step back we simplify the approach to one that is
 124 manageable by a much smaller team.
 125
 126 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 127
 128 As in 2022-08-051
 129 we are already set to submit presentations through multiple Conferences
 130 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 131 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 132 so is accessible to all.
 133
 134 # Extra info to be submitted
 135