nlnet_2022_opf_isa_wg.mdwn

   1 # NL.net proposal
   2
   3 * 2022-08-051
   4 * [[nlnet_2022_opf_isa_wg/discussion]]
   5
   6 ## Project name
   7
   8 Libre-SOC OpenPOWER ISA RFCs
   9
  10 ## Website / wiki
  11
  12 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
  13
  14 # Summary
  15
  16 In earlier NLnet Grants, thanks to EU funding, we developed Draft
  17 SVP64 (a Vector Extension for the Power ISA), around a hundred
  18 new Draft instructions that dramatically improves the Supercomputing-class
  19 Power ISA, a Simulator, thousands
  20 of unit tests and over 350 pages of documentation.  What we could
  21 not do however was submit a Specification to the OpenPOWER ISA
  22 Working Group because the ISA WG was in the process of being
  23 ratified.  That has now been done, and we need to begin the
  24 formal process of writing up "Requests For Change" and submitting
  25 them. The end result will be an extremely powerful Vector ISA suitable
  26 for use in Digitally-Sovereign end-user products.
  27
  28 # Submission to NLnet
  29
  30 Please be short and to the point in your answers; focus primarily on
  31 the what and how, not so much on the why. Add longer descriptions as
  32 attachments (see below). If English isn't your first language, don't
  33 worry - our reviewers don't care about spelling errors, only about
  34 great ideas. We apologise for the inconvenience of having to submit in
  35 English. On the up side, you can be as technical as you need to be (but
  36 you don't have to). Do stay concrete. Use plain text in your reply only,
  37 if you need any HTML to make your point please include this as attachment.
  38
  39 ## Abstract: Can you explain the whole project and its expected outcome(s).
  40
  41 The current NLnet funding to date has allowed Libre-SOC to develop
  42 one of the most powerful Scalable Vector ISAs in the world.
  43 The 25-year-old Power ISA, developed and curated by IBM, was
  44 transferred to the OpenPOWER Foundation, and is the basis on
  45 which, with NLnet EU funding, we have based
  46 Simple-V, the Draft Scalable Vector Extension.
  47
  48 Simple-V *needs* to be submitted to the OPF ISA Working Group,
  49 for formal discussion and inclusion. Given that it is 380
  50 pages we expect this to be done carefully and incrementally.
  51 https://ftp.libre-soc.org/simple_v_spec.pdf
  52
  53 However the
  54 process of submitting RFCs (Requests For Change), at the time of writing,
  55 still has not been publicly announced and opened up. We expect it
  56 to be very soon, but obviously could not begin any RFC Submission
  57 as part of earlier NLnet funding.  The timing is now right.
  58
  59 We will become publicly informed very shortly of the procedures but anticipate
  60 it to include development and submission of Compliance Test Suites
  61 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
  62 as well as ongoing work on the Simulator.
  63
  64 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  65
  66 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  67 and includes
  68
  69 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  70 * the world's first in-place Discrete Cosine Transform algorithm;
  71 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  72  to do an 800,000 transistor fully automated RTL2GDSII
  73 tape-out;
  74 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  75   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  76 * development of an Interoperability "Test API" for Power ISA systems,
  77   with thousands of unit tests.
  78
  79 and much more. The side-benefits alone for EU citizens are enormous.
  80
  81 # Requested Amount
  82
  83 EUR 100,000.
  84
  85 # Explain what the requested budget will be used for?
  86
  87 Time and resource, primarily manpower, to prepare and submit the documentation
  88 to OPF. To give us legal compliance for the development
  89 work carried out over the past four years, as part of the
  90 transfer to the OpenPOWER Foundation.
  91
  92 * ongoing communication with the OpenPOWER Foundation ISA Working Group
  93 * preparation of a large number of RFCs (380 pages total so far) through
  94   the External RFC Process
  95 * for each RFC accepted, work needs to be done with IBM to submit Power ISA Spec
  96   changes
  97 * for each RFC accepted, a Compliance Test Suite must be written
  98 * for each Compliance Test Suite written the results must be
  99   confirmed correct by inspection (hence the Simulator) which has
 100   as we already discovered been quite a lot of work
 101 * Along the way we aim to continue developing the "Test API" which
 102   allows running thousands of unit tests on multiple systems and
 103   cross-checking the results.  Currently we have Simulator, some
 104   "Expected Results", and the Libre-SOC HDL as well as qemu.
 105   We aim to add cavatools, gem5, Microwatt and stand-alone binary
 106   auto-generation for running on IBM POWER9 as well as Libre-SOC
 107   and Microwatt FPGAs.
 108
 109 # Compare your own project with existing or historical efforts.
 110
 111 We are developing a Cray-style Scalable Vector ISA Extension for
 112 the Supercomputing-class Power ISA.  Similar historic ISAs include
 113 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
 114 They are all proprietary systems: Libre-SOC's efforts are entirely
 115 FOSSHW.
 116
 117 Open Scalable Vector ISAs include MRISC32/64 (in early development) and
 118 RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
 119 that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
 120 Additionally, submission of RISCV ISA modifications requires RISCV Foundation
 121 Membership which puts us under impossible conflict of interest with
 122 Full Transparency Conditions not only with NLnet but also with
 123 EU Auditing Requirements.  By direct contrast OPF External RFC Submission
 124 does not require Secrecy.
 125
 126 ## What are significant technical challenges you expect to solve during the project, if any?
 127
 128 The main challenge is one of communication. The majority of the technical
 129 development has been done thanks to NLnet
 130 but it was so complex and comprehensive that it risks overwhelming the ISA
 131 WG Members, whose primary driver has of course been IBM for the past 25
 132 years.
 133
 134 Libre-SOC proposes taking the Power ISA into mainstream computing,
 135 including Video Decode, 3D, GPU workloads, cryptography, and Desktop
 136 and Portable devices, all of which are far different from IBM's traditional
 137 Mainframe-style multi-billion-dollar Supercomputing business.
 138 We therefore have to be both deeply respectful of their achievements, and
 139 non-disruptive to their customer base, but
 140 also appropriately assertive now that the ISA is managed by the OpenPOWER
 141 Foundation.
 142
 143 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 144
 145 Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
 146 is paramount. That said we recognise that no FOSSHW team is going to
 147 manufacture FOSS ASICs in 7nm (unless several billion dollars is available
 148 to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
 149 has been formed by us as an Independent Entity,
 150 which will commercialise Libre-SOC's designs and handle
 151 any Commercially-confidential matters that a Transparency-committed
 152 FOSSHW team simply
 153 cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
 154 from the "other side of the fence", that matters progress smoothly
 155 for IBM and other OPF Members.
 156
 157 RED Semiconductor Ltd will the commercial point of contact for Simple-V
 158 where Organisations are unable to deal with FOSS Entities. This maximises
 159 the broad market benefit of the technology, in line with European Objectives.
 160
 161 We are already set to submit presentations through multiple Conferences
 162 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 163 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 164 so is accessible to all.
 165
 166 # Extra info to be submitted
 167
 168 the budget is high because we honestly do not know yet how much work
 169 IBM and the ISA WG expects us to do.  we do however know that there
 170 will be announcements very soon. If it turns out to be less work
 171 we are more than happy to go with a proportionately smaller budget.