nlnet_2022_opf_isa_wg.mdwn

   1 # NL.net proposal
   2
   3
   4 ## Project name
   5
   6 OpenPOWER ISA RFCs
   7
   8 ## Website / wiki
   9
  10 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
  11
  12 Please be short and to the point in your answers; focus primarily on
  13 the what and how, not so much on the why. Add longer descriptions as
  14 attachments (see below). If English isn't your first language, don't
  15 worry - our reviewers don't care about spelling errors, only about
  16 great ideas. We apologise for the inconvenience of having to submit in
  17 English. On the up side, you can be as technical as you need to be (but
  18 you don't have to). Do stay concrete. Use plain text in your reply only,
  19 if you need any HTML to make your point please include this as attachment.
  20
  21 ## Abstract: Can you explain the whole project and its expected outcome(s).
  22
  23 The current NLnet funding to date has allowed Libre-SOC to develop
  24 one of the most powerful Scalable Vector ISAs in the world.
  25 The 25-year-old Power ISA, developed and curated by IBM, was
  26 transferred to the OpenPOWER Foundation, and is the basis of
  27 Simple-V, the Draft Scalable Vector Extension.
  28
  29 Simple-V *needs* to be submitted to the OPF ISA Working Group,
  30 for formal discussion and inclusion. Given that it is 380
  31 pages we expect this to be done carefully and incrementally.
  32 https://ftp.libre-soc.org/simple_v_spec.pdf
  33
  34 However the
  35 process of submitting Requests For Change, at the time of writing,
  36 still has not been publicly announced and opened up. We expect it
  37 to be very soon, but obviously could not begin any RFC Submission as
  38 part of the earlier NLnet funding.
  39
  40 We will also become informed very shortly of the procedures but anticipate
  41 it to include development and submission of Compliance Test Suites
  42 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
  43 as well as ongoing work on the Simulator.
  44
  45 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  46
  47 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  48 and includes the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  49 the world's first in-place Discrete Cosine Transform algorithm;
  50 Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs) to do an 800,000 transistor fully automated RTL2GDSII
  51 tape-out; the side-benefits alone are enormous.
  52
  53 # Requested Amount
  54
  55 EUR 100,000.
  56
  57 # Explain what the requested budget will be used for?
  58
  59 Time and resource, primarily manpower, to prepare and submit the documentation
  60 to OPF. To give us legal compliance for the development
  61 work carried out over the past four years, as part of the
  62 transfer to the OpenPOWER Foundation.
  63
  64 * ongoing communication with the OpenPOWER Foundation ISA Working Group
  65 * preparation of a large number of RFCs (380 pages total so far) through
  66   the External RFC Process
  67 * for each RFC accepted, work needs to be done with IBM to submit Power ISA Spec
  68   changes
  69 * for each RFC accepted, a Compliance Test Suite must be written
  70 * for each Compliance Test Suite written the results must be
  71   confirmed correct by inspection (hence the Simulator) which has
  72   as we already discovered been quite a lot of work
  73 * Along the way we aim to continue developing the "Test API" which
  74   allows running thousands of unit tests on multiple systems and
  75   cross-checking the results.  Currently we have Simulator, some
  76   "Expected Results", and the Libre-SOC HDL as well as qemu.
  77   We aim to add cavatools, gem5, Microwatt and stand-alone binary
  78   auto-generation for running on IBM POWER9 as well as Libre-SOC
  79   and Microwatt FPGAs.
  80
  81 # Compare your own project with existing or historical efforts.
  82
  83 We are developing a Cray-style Scalable Vector ISA Extension for
  84 the Supercomputing-class Power ISA.  Similar historic ISAs include
  85 Cray YMP1, ETA-19, Cyber CDC 205. More recent is the NEC SX Aurora.
  86 They are all proprietary systems: Libre-SOC's efforts are entirely
  87 FOSSHW.
  88
  89 Open Scalable Vector ISAs include MRISC32/64 (in early development) and
  90 RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
  91 that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
  92 Additionally, submission of RISCV ISA modifications requires RISCV Foundation
  93 Membership which puts us under impossible conflict of interest with
  94 Full Transparency Conditions not only with NLnet but also with
  95 EU Auditing Requirements.  By direct contrast OPF External RFC Submission
  96 does not require Secrecy.
  97
  98 ## What are significant technical challenges you expect to solve during the project, if any?
  99
 100 The main challenge is one of communication. The majority of the technical
 101 development has been done thanks to NLnet
 102 but it was so complex and comprehensive that it risks overwhelming the ISA
 103 WG Members, whose primary driver has of course been IBM for the past 25
 104 years.
 105
 106 Libre-SOC proposes taking the Power ISA into mainstream computing,
 107 including Video Decode, 3D, GPU workloads, cryptography, and Desktop
 108 and Portable devices, all of which are far different from IBM's traditional
 109 Mainframe-style multi-billion-dollar Supercomputing business.
 110 We therefore have to be both deeply respectful of their achievements, and
 111 non-disruptive to their customer base, but
 112 also appropriately assertive now that the ISA is managed by the OpenPOWER
 113 Foundation.
 114
 115 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 116
 117 Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
 118 is paramount. That said we recognise that no FOSSHW team is going to
 119 manufacture FOSS ASICs in 7nm (unless several billion dollars is available
 120 to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
 121 has been formed by us as an Independent Entity,
 122 which will commercialise Libre-SOC's designs and handle
 123 any Commercially-confidential matters that a Transparency-committed
 124 FOSSHW team simply
 125 cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
 126 from the "other side of the fence", that matters progress smoothly
 127 for IBM and other OPF Members.
 128
 129 RED Semiconductor Ltd will the commercial point of contact for Simple-V
 130 where Organisations are unable to deal with FOSS Entities. This maximises
 131 the broad market benefit of the technology.
 132
 133 We are already set to submit presentations through multiple Conferences
 134 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 135 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 136 so is accessible to all.
 137
 138 # Extra info to be submitted
 139
 140 the budget is high because we honestly do not know yet how much work
 141 IBM and the ISA WG expects us to do.  we do however know that there
 142 will be announcements very soon. If it turns out to be less work
 143 we are more than happy to go with a proportionately smaller budget.