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[libreriscv.git] / nlnet_2022_opf_isa_wg.mdwn
1 # NL.net proposal
2
3 * 2022-08-051
4 * [[nlnet_20222_opf_isa_wg/discussion]]
5
6 ## Project name
7
8 Libre-SOC OpenPOWER ISA RFCs
9
10 ## Website / wiki
11
12 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
13
14 Please be short and to the point in your answers; focus primarily on
15 the what and how, not so much on the why. Add longer descriptions as
16 attachments (see below). If English isn't your first language, don't
17 worry - our reviewers don't care about spelling errors, only about
18 great ideas. We apologise for the inconvenience of having to submit in
19 English. On the up side, you can be as technical as you need to be (but
20 you don't have to). Do stay concrete. Use plain text in your reply only,
21 if you need any HTML to make your point please include this as attachment.
22
23 ## Abstract: Can you explain the whole project and its expected outcome(s).
24
25 The current NLnet funding to date has allowed Libre-SOC to develop
26 one of the most powerful Scalable Vector ISAs in the world.
27 The 25-year-old Power ISA, developed and curated by IBM, was
28 transferred to the OpenPOWER Foundation, and is the basis on
29 which, with NLnet EU funding, we have based
30 Simple-V, the Draft Scalable Vector Extension.
31
32 Simple-V *needs* to be submitted to the OPF ISA Working Group,
33 for formal discussion and inclusion. Given that it is 380
34 pages we expect this to be done carefully and incrementally.
35 https://ftp.libre-soc.org/simple_v_spec.pdf
36
37 However the
38 process of submitting RFCs (Requests For Change), at the time of writing,
39 still has not been publicly announced and opened up. We expect it
40 to be very soon, but obviously could not begin any RFC Submission
41 as part of earlier NLnet funding. The timing is now right.
42
43 We will become publicly informed very shortly of the procedures but anticipate
44 it to include development and submission of Compliance Test Suites
45 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
46 as well as ongoing work on the Simulator.
47
48 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
49
50 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
51 and includes
52
53 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
54 * the world's first in-place Discrete Cosine Transform algorithm;
55 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
56 to do an 800,000 transistor fully automated RTL2GDSII
57 tape-out;
58 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
59 ASIC ever taped-out in Europe (and funded by Horizon 2020)
60 * development of an Interoperability "Test API" for Power ISA systems,
61 with thousands of unit tests.
62
63 and much more. The side-benefits alone for EU citizens are enormous.
64
65 # Requested Amount
66
67 EUR 100,000.
68
69 # Explain what the requested budget will be used for?
70
71 Time and resource, primarily manpower, to prepare and submit the documentation
72 to OPF. To give us legal compliance for the development
73 work carried out over the past four years, as part of the
74 transfer to the OpenPOWER Foundation.
75
76 * ongoing communication with the OpenPOWER Foundation ISA Working Group
77 * preparation of a large number of RFCs (380 pages total so far) through
78 the External RFC Process
79 * for each RFC accepted, work needs to be done with IBM to submit Power ISA Spec
80 changes
81 * for each RFC accepted, a Compliance Test Suite must be written
82 * for each Compliance Test Suite written the results must be
83 confirmed correct by inspection (hence the Simulator) which has
84 as we already discovered been quite a lot of work
85 * Along the way we aim to continue developing the "Test API" which
86 allows running thousands of unit tests on multiple systems and
87 cross-checking the results. Currently we have Simulator, some
88 "Expected Results", and the Libre-SOC HDL as well as qemu.
89 We aim to add cavatools, gem5, Microwatt and stand-alone binary
90 auto-generation for running on IBM POWER9 as well as Libre-SOC
91 and Microwatt FPGAs.
92
93 # Compare your own project with existing or historical efforts.
94
95 We are developing a Cray-style Scalable Vector ISA Extension for
96 the Supercomputing-class Power ISA. Similar historic ISAs include
97 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
98 They are all proprietary systems: Libre-SOC's efforts are entirely
99 FOSSHW.
100
101 Open Scalable Vector ISAs include MRISC32/64 (in early development) and
102 RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
103 that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
104 Additionally, submission of RISCV ISA modifications requires RISCV Foundation
105 Membership which puts us under impossible conflict of interest with
106 Full Transparency Conditions not only with NLnet but also with
107 EU Auditing Requirements. By direct contrast OPF External RFC Submission
108 does not require Secrecy.
109
110 ## What are significant technical challenges you expect to solve during the project, if any?
111
112 The main challenge is one of communication. The majority of the technical
113 development has been done thanks to NLnet
114 but it was so complex and comprehensive that it risks overwhelming the ISA
115 WG Members, whose primary driver has of course been IBM for the past 25
116 years.
117
118 Libre-SOC proposes taking the Power ISA into mainstream computing,
119 including Video Decode, 3D, GPU workloads, cryptography, and Desktop
120 and Portable devices, all of which are far different from IBM's traditional
121 Mainframe-style multi-billion-dollar Supercomputing business.
122 We therefore have to be both deeply respectful of their achievements, and
123 non-disruptive to their customer base, but
124 also appropriately assertive now that the ISA is managed by the OpenPOWER
125 Foundation.
126
127 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
128
129 Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
130 is paramount. That said we recognise that no FOSSHW team is going to
131 manufacture FOSS ASICs in 7nm (unless several billion dollars is available
132 to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
133 has been formed by us as an Independent Entity,
134 which will commercialise Libre-SOC's designs and handle
135 any Commercially-confidential matters that a Transparency-committed
136 FOSSHW team simply
137 cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
138 from the "other side of the fence", that matters progress smoothly
139 for IBM and other OPF Members.
140
141 RED Semiconductor Ltd will the commercial point of contact for Simple-V
142 where Organisations are unable to deal with FOSS Entities. This maximises
143 the broad market benefit of the technology, in line with European Objectives.
144
145 We are already set to submit presentations through multiple Conferences
146 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
147 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
148 so is accessible to all.
149
150 # Extra info to be submitted
151
152 the budget is high because we honestly do not know yet how much work
153 IBM and the ISA WG expects us to do. we do however know that there
154 will be announcements very soon. If it turns out to be less work
155 we are more than happy to go with a proportionately smaller budget.