corrections to setvl from debugging
[libreriscv.git] / openpower / isa / simplev.mdwn
1 # setvl
2
3 SVL-Form
4
5 * setvl RT, RA, SVi, vs, ms
6 * setvl. RT, RA, SVi, vs, ms
7
8 Pseudo-code:
9
10 VLimm <- SVi + 1
11 if vs = 1 then
12 if _RA != 0 then
13 VL <- (RA|0)[57:63]
14 else
15 VL <- VLimm[1:7]
16 else
17 VL <- SVSTATE[7:13]
18 if ms = 1 then
19 MVL <- VLimm[1:7]
20 else
21 MVL <- SVSTATE[0:6]
22 if VL > MVL then
23 VL = MVL
24 SVSTATE[0:6] <- MVL
25 SVSTATE[7:13] <- VL
26 RT <- [0]*57 || VL
27
28 Special Registers Altered:
29
30 CR0 (if Rc=1)
31