openpower/isa.mdwn

   1 # ISA Pseudo-code
   2
   3 <!-- this is a test comment -->
   4
   5 ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
   6 the: CPU instructions, register set, memory model, etc, that describe
   7 the way a machine works.
   8
   9 These pages contain (in a strict machine-readable subset of mdwn)
  10 the pseudo-code for all opcodes in the POWER v3.0B Public Spec
  11
  12 * [[isa/bcd]]
  13 * [[isa/branch]]
  14 * [[isa/comparefixed]]
  15 * [[isa/condition]]
  16 * [[isa/fixedarith]]
  17 * [[isa/fixedload]]
  18 * [[isa/fixedlogical]]
  19 * [[isa/fixedshift]]
  20 * [[isa/fixedstore]]
  21 * [[isa/fixedtrap]]
  22 * [[isa/sprset]]
  23 * [[isa/stringldst]]
  24 * [[isa/system]]
  25
  26 FP instructions: useful for testing <http://weitz.de/ieee/>
  27
  28 * [[isa/fpload]]
  29 * [[isa/fpstore]]
  30 * [[isa/fpmove]]
  31 * [[isa/fparith]]
  32 * [[isa/fpcvt]]
  33
  34 Scalar instructions added as part of [[sv/svp64]] development, these are
  35 all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
  36 on Simple-V).
  37 Explanation of the rules for twin register targets
  38 (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
  39
  40 * [[isa/svfixedarith]]
  41 * [[isa/svfparith]]
  42 * [[isa/bitmanip]]
  43 * [[isa/av]] - Audio/Video includes minmax, sum of absolute difference etc.
  44
  45 Scalar "Post-Increment" Draft Load/Store with Update
  46
  47 * [[isa/pifixedload]]
  48 * [[isa/pifixedstore]]
  49 * [[isa/pifpload]]
  50 * [[isa/pifpstore]]
  51
  52 Scalar "Post-Increment" Draft Load/Store with Shift
  53
  54 * [[isa/pifixedloadshift]]
  55 * [[isa/pifixedstoreshift]]
  56 * [[isa/pifploadshift]]
  57 * [[isa/pifpstoreshift]]
  58
  59 Part of the DRAFT Simple-V Specification:
  60
  61 * [[isa/simplev]]
  62
  63 A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
  64
  65 # Pseudocode syntax
  66
  67 The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
  68
  69 The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first).  Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not.  Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax.  Thus the following pseudocode:
  70
  71     if x = 1 then
  72        RT <- 1
  73     else
  74        RT <- 0
  75
  76 results in the parser seeing the following python code:
  77
  78     if x == 1:
  79        RT = 1
  80     else
  81        RT = 0
  82
  83 To support this python-like syntax some of the pseudocode after extraction from the PDF had to be cleaned up and proper indentation added.
  84
  85 Also worth noting as used in the above example: the following operators are used (see section 1.3 "Notation" of v3.0B PDF):
  86
  87 * `<-` assignment, instead of "=" as in python
  88 * `=` equals comparator, instead of "==" as in python
  89 * `||` concatenate, done bitwise, in MSB0 order.
  90 * `>u` for unsigned greater (">" is signed)
  91 * `<u` for unsigned lessthan ("<" is signed)
  92 * X superscript n subscript is instead expressed `[X]*n`
  93 * X subscript n or n:m is expressed as `X[n:m]`
  94
  95 The reason for the addition of the unsigned comparator operators is because numbers in the pseudocode are bitpatterns, not assigned a type or a sign as would normally be done in a standard programming language
  96