openpower/pipeline_operands.mdwn

   1 # XER setting rules
   2
   3 this tells us the conditions under which these bits need to be set.
   4 it therefore defines which registers - where each bit of XER *is*
   5 a separate register - is to be covered by Dependency Matrices.
   6
   7 notation: "COUT" means "carry out bit from result".  therefore COUT[M]
   8 means "the carry out bit in position 32 or 64 of the result".  therefore
   9 in add/subtract this means "the result bit in position 33 or 65".
  10
  11 * bit 32: SO
  12   - addex does not alter SO except when CY=0
  13   - Compare does not alter SO
  14   - any other non-overflowing operation (TBD)
  15   - mtspr will set XER
  16 * bit 33: OV
  17   - XO-form ADD/SUBF/NEG (when OE=1) set OV to test "COUT[M]!=COUT[M+1]"
  18   - addex (when CY=0) set OV to COUT[M]
  19   - XO-form MUL/DIV (when OE=1) set OV="can result fit in target 32/64"
  20   - not altered by Compare
  21   - mtspr will set XER
  22 * bit 34: CA
  23   - add carrying, sub-from carrying, addex, subex - set CA to COUT[M]
  24   - sra - set CA to "any 1-bits shifted out of a negative operand"
  25   - not altered by Compare
  26   - not altered by anything that cannot carry
  27   - mtspr will set XER
  28 * bit 44: OV32
  29   - set whenever OV is set, computed explicitly from 32-bit rather than M-bit
  30 * bit 45: CA32
  31   - set whenever OV is set, computed explicitly from 32-bit rather than M-bit
  32
  33
  34 # Condition Register Pipeline
  35
  36 Input:
  37
  38     64 - Port 1   32 - Port 2
  39     -----------   -----------
  40     RA            CR
  41
  42
  43 Output:
  44
  45     64 - Port 1   32 - Port 2
  46     -----------   -----------
  47     RA            CR
  48
  49 # SPR Register Pipeline
  50
  51 TODO
  52
  53 # TRAP Register Pipeline
  54
  55 TODO
  56
  57 # MUL Register Pipeline
  58
  59 TODO
  60
  61 # DIV/MOD Register Pipeline
  62
  63 TODO
  64
  65 # Branch Register Pipeline
  66
  67 Input:
  68
  69     insn       PC   32-CR  64-SPR1  64-SPR2
  70     ----       --   --     ----     ----
  71     op_b       CIA  xx     xx       xx
  72     op_ba      CIA  xx     xx       xx
  73     op_bl      CIA  xx     xx       xx
  74     op_bla     CIA  xx     xx       xx
  75     op_bc      CIA  CR     xx       CTR
  76     op_bca     CIA  CR     xx       CTR
  77     op_bcl     CIA  CR     xx       CTR
  78     op_bcla    CIA  CR     xx       CTR
  79     op_bclr    CIA  CR     LR       CTR
  80     op_bclrl   CIA  CR     LR       CTR
  81     op_bcctr   CIA  CR     xx       CTR
  82     op_bcctrl  CIA  CR     xx       CTR
  83     op_bctar   CIA  CR     TAR      CTR
  84     op_bctarl  CIA  CR     TAR      CTR
  85
  86 Output:
  87
  88     insn       PC   LR   64-SPR2
  89     ----       --   --   ----
  90     op_b       NIA  xx   xx
  91     op_ba      NIA  xx   xx
  92     op_bl      NIA  xx   xx
  93     op_bla     NIA  xx   xx
  94     op_bc      NIA  xx   CTR
  95     op_bca     NIA  xx   CTR
  96     op_bcl     NIA  xx   CTR
  97     op_bcla    NIA  xx   CTR
  98     op_bclr    NIA  LR   CTR
  99     op_bclrl   NIA  LR   CTR
 100     op_bcctr   NIA  xx   CTR
 101     op_bcctrl  NIA  xx   CTR
 102     op_bctar   NIA  xx   CTR
 103     op_bctarl  NIA  xx   CTR
 104
 105 # System Call Pipeline
 106
 107 Input:
 108
 109     insn       PC   32-CR  64-SPR1  64-SPR2    MSR
 110     ----       --   --     ----     ----       --
 111
 112     op_sc      CIA  xx     xx       xx         MSR
 113     op_scv     CIA  xx     LR       SRR1       MSR
 114     op_rfscv   CIA  xx     LR       CTR        MSR
 115     op_rfid    CIA  xx     SRR0     SRR1       MSR
 116     op_hrfid   CIA  xx     HSRR0    HSRR1      MSR
 117
 118
 119 Output:
 120
 121     insn       PC   LR   64-SPR2  MSR
 122     ----       --   --   ----     ---
 123
 124     op_sc      NIA  xx   xx       MSR
 125     op_scv     NIA  LR   xx       MSR
 126     op_rfscv   NIA  LR   CTR      MSR
 127     op_rfid    NIA  xx   xx       MSR
 128     op_hrfid   NIA  xx   xx       MSR
 129
 130
 131 # Logical Register Pipeline
 132
 133 Input:
 134
 135     64 - Port 1   64 - Port 2  1 - SO  1 - Carry
 136     -----------   -----------  ------  ---------
 137     RA/RS         RB           so      carry_in
 138
 139
 140 Output:
 141
 142     64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
 143     -----------   -----------  ------  ----------------- -----------
 144     RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
 145
 146
 147 # Arithmetic Register Pipeline
 148
 149 Input:
 150
 151     64 - Port 1   64 - Port 2  1 - SO  1 - Carry
 152     -----------   -----------  ------  ---------
 153     RA            RB/immed     so      carry_in
 154
 155
 156 Output:
 157
 158     64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
 159     -----------   -----------  ------  ----------------- -----------
 160     RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
 161
 162
 163 # Shift Register Pipeline
 164
 165 Input:
 166
 167     64 - Port 1   64 - Port 2  64 - Port 3  1 - SO  1 - Carry
 168     -----------   -----------  -----------  ------  ---------
 169     RA            RB/immed     RS           so      carry_in
 170
 171
 172 Output:
 173
 174     64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
 175     -----------   -----------  ------  ----------------- -----------
 176     RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
 177
 178