openpower/simple_v_spec.tex

   1 \documentclass[oneside]{book}
   2 \usepackage{lmodern}
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  10 \usepackage{float}
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  12 \usepackage[useregional]{datetime2}
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  14 \usepackage{ifxetex,ifluatex}
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  16 \ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex
  17   \usepackage[T1]{fontenc}
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  19 \else % if luatex or xelatex
  20   \ifxetex
  21     \usepackage{mathspec}
  22   \else
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  24   \fi
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  26 \fi
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  28 \IfFileExists{upquote.sty}{\usepackage{upquote}}{}
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  33 }{}
  34 \PassOptionsToPackage{hyphens}{url} % url is loaded by hyperref
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  36 \hypersetup{colorlinks=true,
  37             linkcolor=blue,
  38                 filecolor=cyan,
  39                 urlcolor=magenta,
  40             breaklinks=true}
  41 \usepackage[margin=0.9in]{geometry}
  42 \usepackage{color}
  43 \usepackage{fancyvrb}
  44 \newcommand{\VerbBar}{|}
  45 \newcommand{\VERB}{\Verb[commandchars=\\\{\}]}
  46 \DefineVerbatimEnvironment{Highlighting}{Verbatim}{commandchars=\\\{\},xleftmargin=5mm}
  47 % Add ',fontsize=\small' for more characters per line
  48 \newenvironment{Shaded}{}{}
  49 \newcommand{\KeywordTok}[1]{\textcolor[rgb]{0.00,0.44,0.13}{\textbf{#1}}}
  50 \newcommand{\DataTypeTok}[1]{\textcolor[rgb]{0.56,0.13,0.00}{#1}}
  51 \newcommand{\DecValTok}[1]{\textcolor[rgb]{0.25,0.63,0.44}{#1}}
  52 \newcommand{\BaseNTok}[1]{\textcolor[rgb]{0.25,0.63,0.44}{#1}}
  53 \newcommand{\FloatTok}[1]{\textcolor[rgb]{0.25,0.63,0.44}{#1}}
  54 \newcommand{\ConstantTok}[1]{\textcolor[rgb]{0.53,0.00,0.00}{#1}}
  55 \newcommand{\CharTok}[1]{\textcolor[rgb]{0.25,0.44,0.63}{#1}}
  56 \newcommand{\SpecialCharTok}[1]{\textcolor[rgb]{0.25,0.44,0.63}{#1}}
  57 \newcommand{\StringTok}[1]{\textcolor[rgb]{0.25,0.44,0.63}{#1}}
  58 \newcommand{\VerbatimStringTok}[1]{\textcolor[rgb]{0.25,0.44,0.63}{#1}}
  59 \newcommand{\SpecialStringTok}[1]{\textcolor[rgb]{0.73,0.40,0.53}{#1}}
  60 \newcommand{\ImportTok}[1]{#1}
  61 \newcommand{\CommentTok}[1]{\textcolor[rgb]{0.38,0.63,0.69}{\textit{#1}}}
  62 \newcommand{\DocumentationTok}[1]{\textcolor[rgb]{0.73,0.13,0.13}{\textit{#1}}}
  63 \newcommand{\AnnotationTok}[1]{\textcolor[rgb]{0.38,0.63,0.69}{\textbf{\textit{#1}}}}
  64 \newcommand{\CommentVarTok}[1]{\textcolor[rgb]{0.38,0.63,0.69}{\textbf{\textit{#1}}}}
  65 \newcommand{\OtherTok}[1]{\textcolor[rgb]{0.00,0.44,0.13}{#1}}
  66 \newcommand{\FunctionTok}[1]{\textcolor[rgb]{0.02,0.16,0.49}{#1}}
  67 \newcommand{\VariableTok}[1]{\textcolor[rgb]{0.10,0.09,0.49}{#1}}
  68 \newcommand{\ControlFlowTok}[1]{\textcolor[rgb]{0.00,0.44,0.13}{\textbf{#1}}}
  69 \newcommand{\OperatorTok}[1]{\textcolor[rgb]{0.40,0.40,0.40}{#1}}
  70 \newcommand{\BuiltInTok}[1]{#1}
  71 \newcommand{\ExtensionTok}[1]{#1}
  72 \newcommand{\PreprocessorTok}[1]{\textcolor[rgb]{0.74,0.48,0.00}{#1}}
  73 \newcommand{\AttributeTok}[1]{\textcolor[rgb]{0.49,0.56,0.16}{#1}}
  74 \newcommand{\RegionMarkerTok}[1]{#1}
  75 \newcommand{\InformationTok}[1]{\textcolor[rgb]{0.38,0.63,0.69}{\textbf{\textit{#1}}}}
  76 \newcommand{\WarningTok}[1]{\textcolor[rgb]{0.38,0.63,0.69}{\textbf{\textit{#1}}}}
  77 \newcommand{\AlertTok}[1]{\textcolor[rgb]{1.00,0.00,0.00}{\textbf{#1}}}
  78 \newcommand{\ErrorTok}[1]{\textcolor[rgb]{1.00,0.00,0.00}{\textbf{#1}}}
  79 \newcommand{\NormalTok}[1]{#1}
  80
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  82 % https://gist.github.com/bgeron/72ebbacf5930537022079d9953f15713
  83 \usepackage{newunicodechar}
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  85
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  99 \usepackage{longtable,booktabs}
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 121 \fi
 122
 123 % set default figure placement to htbp
 124 \makeatletter\@addtoreset{chapter}{part}\makeatother%
 125 \def\fps@figure{htbp}
 126 \makeatother
 127
 128 % graphics path for primer
 129 \graphicspath{ {svp64-primer/img/} }
 130
 131 \date{}
 132
 133 \begin{document}
 134
 135 \chapter*{Preamble}
 136 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 137
 138 \textbf{Last modified date: \today}
 139
 140 This document is an auto-generated version of the Draft SVP64
 141 Specification available at
 142
 143 \begin{verbatim}
 144      https://libre-soc.org/openpower/sv
 145 \end{verbatim}
 146
 147 for which the source code is available at
 148
 149 \begin{verbatim}
 150      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 151 \end{verbatim}
 152
 153 This PDF may be created with "make pdf" from the following file:
 154
 155 \begin{verbatim}
 156     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 157 \end{verbatim}
 158
 159 by executing the following commands:
 160
 161 \begin{verbatim}
 162     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 163     cd libresoc/libresoc/openpower
 164     make pdf
 165 \end{verbatim}
 166
 167 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 168 sponsored by the NLnet Foundation and NGI POINTER under
 169 EU Grants 871528 and 957073.
 170
 171 Simple-V is in DRAFT Status and will be submitted publicly
 172 (non-confidentially) through the OPF ISA WG "External Submissions"
 173 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 174 Programme, requires full transparency.
 175
 176 As this document is under continuous rapid revision please check frequently
 177 at:
 178
 179 \begin{verbatim}
 180     https://ftp.libre-soc.org/simple_v_spec.pdf
 181 \end{verbatim}
 182
 183 \subsection*{Contacts}
 184 For questions, comments, and clarification, please contact the following:
 185 \begin{itemize}
 186     \itemsep -0.3em
 187     \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
 188     \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
 189     Semiconductor Ltd Director - lkcl@lkcl.net
 190     \item David Calderwood - Red Semiconductor Ltd Director -
 191     djac@calderwoodhan.com
 192     \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
 193     Director - toshaan@vantosh.com
 194     \item Konstantinos Margaritis -  Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs  - konstantinos@vectorcamp.gr
 195     \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
 196     \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
 197     \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
 198     \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
 199 \end{itemize}
 200
 201 \newpage
 202 \subsection*{Executive Summary}
 203 \hypertarget{svux2fexecutive_summary}{}
 204 \input{tex_out/executive_summary.tex}
 205
 206 \newpage
 207 \begin{landscape}
 208 \addcontentsline{toc}{chapter}{Comparison Table} \markboth{INTRODUCTION}{}
 209 \hypertarget{svux2fcomparison_table}{}
 210 {
 211 \fontsize{6}{8}\selectfont
 212 \input{tex_out/comparison_table.tex}
 213 }
 214 \end{landscape}
 215
 216 \part{Scalable Vectors Primer}
 217 \input{svp64-primer/acronyms}
 218 %\chapter*{Executive Summary}
 219 \include{svp64-primer/summary}
 220 \bibliography{svp64-primer/references}
 221 \bibliographystyle{ieeetr}
 222
 223 \tableofcontents
 224
 225 % Part II
 226 \part{Scalable Vectors for the Power ISA}
 227
 228
 229 \chapter{Fields and Forms}
 230 \hypertarget{svux2ffields}{}
 231 \input{tex_out/fields.tex}
 232 \chapter{Scalable Vectors for the Power ISA}
 233 \hypertarget{svux2fscalvecpowisa}{}
 234 \hypertarget{SVux7csv}{}
 235 \input{tex_out/sv.tex}
 236 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 237 \input{tex_out/vector_isas.tex}
 238 \chapter{Overview}\hypertarget{svux2foverview}{}
 239 \input{tex_out/overview.tex}
 240 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 241 \input{tex_out/compliancy_levels.tex}
 242 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 243 \input{tex_out/svp64.tex}
 244 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 245 \input{tex_out/sprs.tex}
 246 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 247 \input{tex_out/normal.tex}
 248 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 249 \input{tex_out/ldst.tex}
 250 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 251 \input{tex_out/cr_ops.tex}
 252 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 253 \input{tex_out/branches.tex}
 254 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 255 \input{tex_out/setvl.tex}
 256 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 257 \input{tex_out/svstep.tex}
 258 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 259 \input{tex_out/remap.tex}
 260 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 261 \input{tex_out/mv_swizzle.tex}
 262 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 263 \input{tex_out/mv_vec.tex}
 264
 265 \begin{appendices}
 266 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 267 \hypertarget{svux2fsvp64ux2fappendix}{}
 268 \input{tex_out/svp64_appendix.tex}
 269 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 270 \input{tex_out/svp64_quirks.tex}
 271 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 272 \input{tex_out/remap_appendix.tex}
 273 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 274 \input{tex_out/pseudocode_simplev.tex}
 275 \chapter{Simple-V Analysis}\hypertarget{svux2fsv_analysis}{}
 276 \input{tex_out/sv_analysis.tex}
 277
 278 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 279 \begin{landscape}
 280 {
 281 \fontsize{7}{9}\selectfont
 282 \input{tex_out/opcode_regs_deduped.tex}
 283 }
 284 \end{landscape}
 285
 286 \end{appendices}
 287
 288 % Part III
 289 \part{Scalar Instructions}
 290
 291 \chapter*{Preamble}{}
 292
 293 As explained in the Simple-V introduction
 294 these are all intentionally and specifically Scalar instructions.
 295 Each section is free-standing, has no connection, dependence or
 296 relationship to any other section, including no direct critical dependence
 297 either way on Simple-V.
 298 They have with almost no exceptions been specifically crafted to
 299 have a justification for their inclusion in the Power ISA as Scalar
 300 instructions purely on their own merit.
 301
 302 \begin{itemize}
 303         \item The biginteger multiply-and-add instruction is similar
 304         to Intel's mulx in that it produces a pair of results.
 305         \item JavaScript(tm) rounding is present in ARM as fjcvtzs
 306         and would save an astounding 35 instructions with 5 branches.
 307         \item Whilst there exist CR bit manipulation and copying
 308         instructions there are no CR Field manipulation instructions,
 309         putting pressure on GPRs if several CR fits need to be analysed.
 310         \item one single instruction, bmask, is proposed that covers
 311         the whole of x86 BMI1 and AMD TBM, combined, and provides more.
 312 \end{itemize}
 313
 314 All of these have nothing to do with Simple-V at all: they make
 315 the Power ISA better at modern general-purpose compute, bringing
 316 it up-to-date.
 317
 318 That said: by a wonderful coincidence, should they be included, then
 319 Simple-V's capabilities increase significantly. For example the CRweird
 320 instructions combined with the bitmanip instructions, alongside
 321 Vectorised Rc=1 turn CR Fields into
 322 extremely powerful Predicate masks. bmask not only
 323 covers the BMI and TBM instructions of Intel and AMD it also
 324 includes the RVV set-before-first and set-after-first instructions.
 325
 326 The clean and clear separation between Vectorisation Prefix and Scalar
 327 Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
 328 to benefit.  It also makes proposal much easier, as there is no
 329 inter-dependence.
 330
 331 It is however important to note that the rationale for these instructions
 332 comes from a more general-purpose modern computing paradigm that is
 333 outside of IBM's much more focussed and specialist traditional customer
 334 base. We deeply respect IBM's curator role of the Power ISA of the past 25
 335 years as much as we appreciate their courage in transferring that role
 336 to the OpenPOWER Foundation ISA Working Group.
 337
 338 \chapter{SV Vector-assist Scalar ops}\hypertarget{svux2fvector_ops}{}
 339 \input{tex_out/vector_ops.tex}
 340 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 341 \hypertarget{cr_int_predication}{}
 342 \input{tex_out/cr_int_predication.tex}
 343 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 344 \input{tex_out/bitmanip.tex}
 345 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 346 \input{tex_out/int_fp_mv.tex}
 347 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 348 \input{tex_out/fclass.tex}
 349 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 350 \hypertarget{av_opcodes}{}
 351 \input{tex_out/av_opcodes.tex}
 352 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 353 \input{tex_out/big_integer.tex}
 354 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 355 \input{tex_out/transcendentals.tex}
 356 %\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 357 %\input{tex_out/atomics.tex}
 358
 359 \begin{appendices}
 360 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 361 \input{tex_out/big_integer_analysis.tex}
 362 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 363 \input{tex_out/pseudocode_bitmanip.tex}
 364 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 365 \input{tex_out/pseudocode_svfparith.tex}
 366 \chapter{Fixed Point pseudocode}
 367 \hypertarget{isaux2fsvfixedarith}{}
 368 \input{tex_out/pseudocode_svfixedarith.tex}
 369 \end{appendices}
 370
 371 % Part IV
 372 \part{Scalar Power ISA pseudocode}
 373 \backmatter % temporary fix for too many appenfices
 374 %\setcounter{chapter}{0}
 375 %\renewcommand{\thechapter}{\Alph{chapter}}
 376
 377 \chapter*{Preamble}
 378 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 379
 380 This section contains updated pseudocode from the Power ISA Specification
 381 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 382 found and reported as a direct result due to actually running the
 383 pseudocode as executable code in a Simulator.
 384 A Formal Correctness Proof Research Paper written by Boris
 385 Shingarov.
 386
 387 Additionally, with SVP64 performing element-width over-rides it is the
 388 \textit{Scalar} pseudocode that needs adapting to variable-length
 389 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 390 respect \textit{except} for an XLEN as part of the Simple-V Specification
 391 is completely pointless and a waste of time: the updates to include
 392 XLEN need to be part
 393 of the Scalar Power ISA Specification.  This has the added benefit
 394 that it makes life much easier for 32-bit implementors, and has an
 395 additional benefit of making it possible for the Scalar Power ISA
 396 to extend to 128-bit in future (like RV128).
 397
 398 \begin{appendices}
 399 \chapter{Binary Coded Decimal pseudocode}
 400 \hypertarget{svux2fpseudocode_bcd}{}
 401 \input{tex_out/pseudocode_bcd.tex}
 402 \chapter{Branch pseudocode}
 403 \hypertarget{openpowerux2fisaux2fbranch}{}
 404 \hypertarget{svux2fpseudocode_branch}{}
 405 \input{tex_out/pseudocode_branch.tex}
 406 \chapter{Fixed Point Compare pseudocode}
 407 \hypertarget{svux2fpseudocode_comparefixed}{}
 408 \input{tex_out/pseudocode_comparefixed.tex}
 409 \chapter{Condition Register pseudocode}
 410 \hypertarget{svux2fpseudocode_condition}{}
 411 \input{tex_out/pseudocode_condition.tex}
 412
 413 \chapter{Fixed Point Arithmetic pseudocode}
 414 \hypertarget{svux2fpseudocode_fixedarith}{}
 415 \input{tex_out/pseudocode_fixedarith.tex}
 416 \chapter{Fixed Point Load pseudocode}
 417 \hypertarget{svux2fpseudocode_fixedload}{}
 418 \input{tex_out/pseudocode_fixedload.tex}
 419 \chapter{Fixed Point Logical pseudocode}
 420 \hypertarget{svux2fpseudocode_fixedlogical}{}
 421 \input{tex_out/pseudocode_fixedlogical.tex}
 422 \chapter{Fixed Point Rotate pseudocode}
 423 \hypertarget{svux2fpseudocode_fixedshift}{}
 424 \input{tex_out/pseudocode_fixedshift.tex}
 425
 426 \chapter{Fixed Point Store pseudocode}
 427 \hypertarget{svux2fpseudocode_fixedstore}{}
 428 \input{tex_out/pseudocode_fixedstore.tex}
 429 \chapter{Fixed Point Trap pseudocode}
 430 \hypertarget{svux2fpseudocode_fixedtrap}{}
 431 \input{tex_out/pseudocode_fixedtrap.tex}
 432 \chapter{Special Purpose Register pseudocode}
 433 \hypertarget{svux2fpseudocode_sprset}{}
 434 \input{tex_out/pseudocode_sprset.tex}
 435 \chapter{String Load/Store pseudocode}
 436 \hypertarget{svux2fpseudocode_stringldst}{}
 437 \input{tex_out/pseudocode_stringldst.tex}
 438 \chapter{System Call pseudocode}
 439 \hypertarget{svux2fpseudocode_system}{}
 440 \input{tex_out/pseudocode_system.tex}
 441
 442 \chapter{Floating Point Load pseudocode}
 443 \hypertarget{svux2fpseudocode_fpload}{}
 444 \input{tex_out/pseudocode_fpload.tex}
 445 \chapter{Floating Point Store pseudocode}
 446 \hypertarget{svux2fpseudocode_fpstore}{}
 447 \input{tex_out/pseudocode_fpstore.tex}
 448 \chapter{Floating Point Move pseudocode}
 449 \hypertarget{svux2fpseudocode_fpmove}{}
 450 \input{tex_out/pseudocode_fpmove.tex}
 451 \chapter{Floating Point Arithmetic pseudocode}
 452 \hypertarget{svux2fpseudocode_fparith}{}
 453 \input{tex_out/pseudocode_fparith.tex}
 454 \chapter{Floating Point Integer Conversion pseudocode}
 455 \hypertarget{svux2fpseudocode_fpcvt}{}
 456 \input{tex_out/pseudocode_fpcvt.tex}
 457
 458 \end{appendices}
 459
 460
 461
 462
 463 \end{document}