7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
10 * binutils <https://bugs.libre-soc.org/show_bug.cgi?id=836>
11 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
17 pseudocode: [[openpower/isa/bitmanip]]
19 this extension amalgamates bitmanipulation primitives from many sources,
20 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
21 Also included are DSP/Multimedia operations suitable for Audio/Video.
22 Vectorisation and SIMD are removed: these are straight scalar (element)
23 operations making them suitable for embedded applications. Vectorisation
24 Context is provided by [[openpower/sv]].
26 When combined with SV, scalar variants of bitmanip operations found in
27 VSX are added so that the Packed SIMD aspects of VSX may be retired as
28 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
29 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
30 or embedded scenarios.
32 ternlogv is experimental and is the only operation that may be considered
33 a "Packed SIMD". It is added as a variant of the already well-justified
34 ternlog operation (done in AVX512 as an immediate only) "because it
35 looks fun". As it is based on the LUT4 concept it will allow accelerated
36 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
37 achieve similar objectives.
39 general-purpose Galois Field 2^M operations are added so as to avoid
40 huge custom opcode proliferation across many areas of Computer Science.
41 however for convenience and also to avoid setup costs, some of the more
42 common operations (clmul, crc32) are also added. The expectation is
43 that these operations would all be covered by the same pipeline.
45 note that there are brownfield spaces below that could incorporate
46 some of the set-before-first and other scalar operations listed in
48 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
49 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
53 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
54 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
55 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
56 * <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
58 [[!inline pages="openpower/sv/draft_opcode_tables" quick="yes" raw="yes" ]]
60 # binary and ternary bitops
62 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
63 bits from each input, concatenate them and perform a lookup into a
64 table using an 8-8-bit immediate (for the ternary instructions), or in
65 another register (4-bit for the binary instructions). The binary lookup
66 instructions have CR Field lookup variants due to CR Fields being 4 bit.
69 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
74 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
75 | -- | -- | --- | --- | ----- | --- |--|
76 | NN | RT | RA | RB | im0-7 | 00 |Rc|
79 idx = c << 2 | b << 1 | a
80 return imm[idx] # idx by LSB0 order
83 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
87 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
88 lookup table is 4 bits wide not 8 bits, and secondly the lookup
89 table comes from a register not an immediate.
91 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
92 | -- | -- | --- | --- | ----- |--------|---------|
93 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
94 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
96 For binlut, the 4-bit LUT may be selected from either the high nibble
97 or the low nibble of the first byte of RC:
101 return imm[idx] # idx by LSB0 order
103 imm = (RC>>(nh*4))&0b1111
105 RT[i] = lut2(imm, RB[i], RA[i])
107 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
110 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
112 When Vectorised with SVP64, as usual both source and destination may be
115 *Programmer's note: a dynamic ternary lookup may be synthesised from
116 a pair of `binlut` instructions followed by a `ternlogi` to select which
117 to merge. Use `nh` to select which nibble to use as the lookup table
118 from the RC source register (`nh=1` nibble high), i.e. keeping
119 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
124 another mode selection would be CRs not Ints.
128 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
129 |----|----|----|-----|-----|-----|-----|-----|---|
130 | NN | BF | msk|BFA | msk | BFB | TLI | XO |TLI|
133 a,b,c = CRs[BF][i], CRs[BFA][i], CRs[BFB][i])
134 if msk[i] CRs[BF][i] = lut3(imm, a, b, c)
136 This instruction is remarkably similar to the existing crops, `crand` etc.
137 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
138 is the ternary LUT version of crops, having an 8-bit LUT. However it
139 is an overwrite instruction in order to save on register file ports,
140 due to the mask requiring the contents of the BF to be both read and
143 Programmer's note: This instruction is useful when combined with Matrix REMAP
144 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
145 applications in Computer Science.
149 With ternary (LUT3) dynamic instructions being very costly,
150 and CR Fields being only 4 bit, a binary (LUT2) variant is better
154 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
155 |----|----|----|-----|-----|-----|-----|-----|---|
156 | NN | BF | msk|BFA | msk | BFB | // | XO | //|
159 a,b = CRs[BF][i], CRs[BF][i])
160 if msk[i] CRs[BF][i] = lut2(CRs[BFB], a, b)
162 When SVP64 Vectorised any of the 4 operands may be Scalar or
163 Vector, including `BFB` meaning that multiple different dynamic
164 lookups may be performed with a single instruction. Note that
165 this instruction is deliberately an overwrite in order to reduce
166 the number of register file ports required: like `crternlogi`
167 the contents of `BF` **must** be read due to the mask only
168 writing back to non-masked-out bits of `BF`.
170 *Programmer's note: just as with binlut and ternlogi, a pair
171 of crbinlog instructions followed by a merging crternlogi may
172 be deployed to synthesise dynamic ternary (LUT3) CR Field
179 required for the [[sv/av_opcodes]]
181 signed and unsigned min/max for integer. this is sort-of partly
182 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
183 is one of the sources, but not both signed and unsigned. when the dest
184 is also one of the srces and the mv fails due to the CR bittest failing
185 this will only overwrite the dest where the src is greater (or less).
187 signed/unsigned min/max gives more flexibility.
189 \[un]signed min/max instructions are specifically needed for vector reduce min/max operations which are pretty common.
193 * XO=0001001110, itype=0b00 min, unsigned
194 * XO=0101001110, itype=0b01 min, signed
195 * XO=0011001110, itype=0b10 max, unsigned
196 * XO=0111001110, itype=0b11 max, signed
200 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
201 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
203 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
204 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
206 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
207 { return rs1 < rs2 ? rs1 : rs2;
209 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
210 { return rs1 > rs2 ? rs1 : rs2;
216 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
220 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
221 return (rs1 + rs2 + 1) >> 1:
227 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
231 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
232 return (src1 > src2) ? (src1-src2) : (src2-src1)
238 required for the [[sv/av_opcodes]], these are needed for motion estimation.
239 both are overwrite on RS.
242 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
243 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
245 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
246 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
250 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
251 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
252 SVP64 designation from RS-as-dest. This gives a limited range of
253 non-overwrite capability.
255 # shift-and-add <a name="shift-add"> </a>
257 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
258 Too complex to add more LD/ST, a compromise is to add shift-and-add.
259 Replaces a pair of explicit instructions in hot-loops.
263 |0 |6 |11 |15 |16 |21 |23 |31 |
264 | PO | RT | RA | RB |sm | XO |Rc |
271 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
273 Pseudo-code (shadduw):
275 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
277 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
280 uint_xlen_t shadd(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
282 return (RB << (sm+1)) + RA;
285 uint_xlen_t shadduw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
286 uint_xlen_t n = RB & 0xFFFFFFFF;
288 return (n << (sm+1)) + RA;
294 based on RV bitmanip singlebit set, instruction format similar to shift
295 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
296 rldicl but only immediate version). however bitmask-invert is not,
297 and set/clr are not covered, although they can use the same Shift ALU.
299 bmext (RB) version is not the same as rldicl because bmext is a right
300 shift by RC, where rldicl is a left rotate. for the immediate version
301 this does not matter, so a bmexti is not required. bmrev however there
302 is no direct equivalent and consequently a bmrevi is required.
304 bmset (register for mask amount) is particularly useful for creating
305 predicate masks where the length is a dynamic runtime quantity.
306 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
307 in a single instruction without needing to initialise or depend on any
310 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
311 | -- | -- | --- | --- | --- | ------- |--| ----- |
312 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
314 Immediate-variant is an overwrite form:
316 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
317 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
318 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
324 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
325 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
330 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
331 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
332 return mask_a ^ mask_b
335 uint_xlen_t bmset(RS, RB, sh)
337 int shamt = RB & (XLEN - 1);
339 return RS | (mask << shamt);
342 uint_xlen_t bmclr(RS, RB, sh)
344 int shamt = RB & (XLEN - 1);
346 return RS & ~(mask << shamt);
349 uint_xlen_t bminv(RS, RB, sh)
351 int shamt = RB & (XLEN - 1);
353 return RS ^ (mask << shamt);
356 uint_xlen_t bmext(RS, RB, sh)
358 int shamt = RB & (XLEN - 1);
360 return mask & (RS >> shamt);
364 bitmask extract with reverse. can be done by bit-order-inverting all
365 of RB and getting bits of RB from the opposite end.
367 when RA is zero, no shift occurs. this makes bmextrev useful for
368 simply reversing all bits of a register.
372 rev[0:msb] = rb[msb:0];
375 uint_xlen_t bmrevi(RA, RB, sh)
378 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
379 shamt = (XLEN-1)-shamt; # shift other end
380 brb = bitreverse(GPR(RB)) # swap LSB-MSB
382 return mask & (brb >> shamt);
385 uint_xlen_t bmrev(RA, RB, RC) {
386 return bmrevi(RA, RB, GPR(RC) & 0b111111);
390 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
391 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
392 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
394 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
395 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
396 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
398 # grevlut <a name="grevlut"> </a>
400 generalised reverse combined with a pair of LUT2s and allowing
401 a constant `0b0101...0101` when RA=0, and an option to invert
402 (including when RA=0, giving a constant 0b1010...1010 as the
403 initial value) provides a wide range of instructions
404 and a means to set hundreds of regular 64 bit patterns with one
405 single 32 bit instruction.
407 the two LUT2s are applied left-half (when not swapping)
408 and right-half (when swapping) so as to allow a wider
411 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
413 * A value of `0b11001010` for the immediate provides
414 the functionality of a standard "grev".
415 * `0b11101110` provides gorc
417 grevlut should be arranged so as to produce the constants
418 needed to put into bext (bitextract) so as in turn to
419 be able to emulate x86 pmovmask instructions
420 <https://www.felixcloutier.com/x86/pmovmskb>.
421 This only requires 2 instructions (grevlut, bext).
423 Note that if the mask is required to be placed
424 directly into CR Fields (for use as CR Predicate
425 masks rather than a integer mask) then sv.cmpi or sv.ori
426 may be used instead, bearing in mind that sv.ori
427 is a 64-bit instruction, and `VL` must have been
428 set to the required length:
430 sv.ori./elwid=8 r10.v, r10.v, 0
432 The following settings provide the required mask constants:
434 | RA=0 | RB | imm | iv | result |
435 | ------- | ------- | ---------- | -- | ---------- |
436 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
437 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
438 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
439 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
440 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
441 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
443 Better diagram showing the correct ordering of shamt (RB). A LUT2
444 is applied to all locations marked in red using the first 4
445 bits of the immediate, and a separate LUT2 applied to all
446 locations in green using the upper 4 bits of the immediate.
448 <img src="/openpower/sv/grevlut.png" width=700 />
450 demo code [[openpower/sv/grevlut.py]]
455 return imm[idx] # idx by LSB0 order
457 dorow(imm8, step_i, chunksize, us32b):
458 for j in 0 to 31 if is32b else 63:
459 if (j&chunk_size) == 0
463 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
466 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
468 uint64_t x = 0x5555_5555_5555_5555;
469 if (RA != 0) x = GPR(RA);
471 int shamt = RB & 31 if is32b else 63
472 for i in 0 to (6-is32b)
474 if (shamt & step) x = dorow(imm, x, step, is32b)
479 A variant may specify different LUT-pairs per row,
480 using one byte of RB for each. If it is desired that
481 a particular row-crossover shall not be applied it is
482 a simple matter to set the appropriate LUT-pair in RB
483 to effect an identity transform for that row (`0b11001010`).
486 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
488 uint64_t x = 0x5555_5555_5555_5555;
489 if (RA != 0) x = GPR(RA);
491 for i in 0 to (6-is32b)
493 imm = (RB>>(i*8))&0xff
494 x = dorow(imm, x, step, is32b)
500 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
501 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
502 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
503 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
505 An equivalent to `grevlogw` may be synthesised by setting the
506 appropriate bits in RB to set the top half of RT to zero.
507 Thus an explicit grevlogw instruction is not necessary.
511 based on RV bitmanip.
513 RA contains a vector of indices to select parts of RB to be
514 copied to RT. The immediate-variant allows up to an 8 bit
515 pattern (repeated) to be targetted at different parts of RT.
517 xperm shares some similarity with one of the uses of bmator
518 in that xperm indices are binary addressing where bitmator
519 may be considered to be unary addressing.
522 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
525 uint_xlen_t sz = 1LL << sz_log2;
526 uint_xlen_t mask = (1LL << sz) - 1;
527 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
528 for (int i = 0; i < XLEN; i += sz) {
529 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
531 r |= ((RB >> pos) & mask) << i;
535 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
538 uint_xlen_t sz = 1LL << sz_log2;
539 uint_xlen_t mask = (1LL << sz) - 1;
540 for (int i = 0; i < XLEN; i += sz) {
541 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
543 r |= ((RB >> pos) & mask) << i;
547 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
548 { return xperm(RA, RB, 2); }
549 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
550 { return xperm(RA, RB, 3); }
551 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
552 { return xperm(RA, RB, 4); }
553 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
554 { return xperm(RA, RB, 5); }
559 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
560 as GF2P8AFFINEQB. uses:
562 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
563 * SM4, Reed Solomon, RAID6
564 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
565 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
566 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
568 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
569 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
570 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
574 uint64_t bmatflip(uint64_t RA)
583 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
585 uint64_t RAt = bmatflip(RA);
586 uint8_t u[8]; // rows of RS
587 uint8_t v[8]; // cols of RA
588 for (int i = 0; i < 8; i++) {
593 for (int i = 0; i < 64; i++) {
594 bit = (imm >> (i%8)) & 1;
595 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
601 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
602 return bmatxori(RA, RB, 0xff)
605 uint64_t bmator(uint64_t RA, uint64_t RB) {
607 uint64_t RBt = bmatflip(RB);
608 uint8_t u[8]; // rows of RA
609 uint8_t v[8]; // cols of RB
610 for (int i = 0; i < 8; i++) {
615 for (int i = 0; i < 64; i++) {
616 if ((u[i / 8] & v[i % 8]) != 0)
622 uint64_t bmatand(uint64_t RA, uint64_t RB) {
624 uint64_t RBt = bmatflip(RB);
625 uint8_t u[8]; // rows of RA
626 uint8_t v[8]; // cols of RB
627 for (int i = 0; i < 8; i++) {
632 for (int i = 0; i < 64; i++) {
633 if ((u[i / 8] & v[i % 8]) == 0xff)
640 # Introduction to Carry-less and GF arithmetic
642 * obligatory xkcd <https://xkcd.com/2595/>
644 There are three completely separate types of Galois-Field-based arithmetic
645 that we implement which are not well explained even in introductory
646 literature. A slightly oversimplified explanation is followed by more
647 accurate descriptions:
649 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
650 but is accidentally referred to as GF(2) - see below as to why.
651 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
653 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
654 (2^N) and a second "reducing" polynomial (similar to a prime number), these
655 are said to be GF(2^N) arithmetic.
657 further detailed and more precise explanations are provided below
659 * **Polynomials with coefficients in `GF(2)`**
660 (aka. Carry-less arithmetic -- the `cl*` instructions).
661 This isn't actually a Galois Field, but its coefficients are. This is
662 basically binary integer addition, subtraction, and multiplication like
663 usual, except that carries aren't propagated at all, effectively turning
664 both addition and subtraction into the bitwise xor operation. Division and
665 remainder are defined to match how addition and multiplication works.
666 * **Galois Fields with a prime size**
667 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
668 This is basically just the integers mod `p`.
669 * **Galois Fields with a power-of-a-prime size**
670 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
672 We only implement these for `p == 2`, called Binary Galois Fields
673 (`GF(2^n)` -- the `gfb*` instructions).
674 For any prime `p`, `GF(p^n)` is implemented as polynomials with
675 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
676 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
677 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
678 Polynomial must be an irreducable polynomial (like primes, but for
679 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
680 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
681 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
682 polynomials used to implement `GF(p^n)`.
684 Many implementations and much of the literature do not make a clear
685 distinction between these three categories, which makes it confusing
686 to understand what their purpose and value is.
688 * carry-less multiply is extremely common and is used for the ubiquitous
689 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
690 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
691 has significant uses throughout cryptography
692 * GF(p) is the basis again of a significant quantity of algorithms
693 (TODO, list them, jacob knows what they are), even though the
694 modulo is limited to be below 64-bit (size of a scalar int)
696 # Instructions for Carry-less Operations
698 aka. Polynomials with coefficients in `GF(2)`
700 Carry-less addition/subtraction is simply XOR, so a `cladd`
701 instruction is not provided since the `xor[i]` instruction can be used instead.
703 These are operations on polynomials with coefficients in `GF(2)`, with the
704 polynomial's coefficients packed into integers with the following algorithm:
707 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
710 ## Carry-less Multiply Instructions
713 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
714 <https://www.felixcloutier.com/x86/pclmulqdq> and
715 <https://en.m.wikipedia.org/wiki/Carry-less_product>
717 They are worth adding as their own non-overwrite operations
718 (in the same pipeline).
720 ### `clmul` Carry-less Multiply
723 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
726 ### `clmulh` Carry-less Multiply High
729 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
732 ### `clmulr` Carry-less Multiply (Reversed)
734 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
738 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
741 ## `clmadd` Carry-less Multiply-Add
744 clmadd RT, RA, RB, RC
748 (RT) = clmul((RA), (RB)) ^ (RC)
751 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
753 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
754 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
755 to avoid the need for a temp register. RS is written to as well as RT.
757 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
758 definition of the Inverse Discrete Fourier Transform involves calculating a
759 multiplicative inverse, which may not exist in every Ring, therefore the
760 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
761 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
762 TODO: check with someone who knows for sure if that's correct.)
765 cltmadd RT, RA, RB, RC
768 TODO: add link to explanation for where `RS` comes from.
773 # read all inputs before writing to any outputs in case
774 # an input overlaps with an output register.
775 (RT) = clmul(a, (RB)) ^ c
779 ## `cldivrem` Carry-less Division and Remainder
781 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
782 for other instructions.
785 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
788 ## `cldiv` Carry-less Division
797 q, r = cldivrem(n, d, width=XLEN)
801 ## `clrem` Carry-less Remainder
810 q, r = cldivrem(n, d, width=XLEN)
814 # Instructions for Binary Galois Fields `GF(2^m)`
818 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
819 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
820 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
822 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
823 instruction is not provided since the `xor[i]` instruction can be used instead.
825 ## `GFBREDPOLY` SPR -- Reducing Polynomial
827 In order to save registers and to make operations orthogonal with standard
828 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
829 This also allows hardware to pre-compute useful parameters (such as the
830 degree, or look-up tables) based on the reducing polynomial, and store them
831 alongside the SPR in hidden registers, only recomputing them whenever the SPR
832 is written to, rather than having to recompute those values for every
835 Because Galois Fields require the reducing polynomial to be an irreducible
836 polynomial, that guarantees that any polynomial of `degree > 1` must have
837 the LSB set, since otherwise it would be divisible by the polynomial `x`,
838 making it reducible, making whatever we're working on no longer a Field.
839 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
842 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
845 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
847 unless this is an immediate op, `mtspr` is completely sufficient.
850 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
853 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
860 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
863 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
866 gfbmadd RT, RA, RB, RC
870 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
873 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
875 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
876 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
877 for a temp register. RS is written to as well as RT.
880 gfbtmadd RT, RA, RB, RC
883 TODO: add link to explanation for where `RS` comes from.
888 # read all inputs before writing to any outputs in case
889 # an input overlaps with an output register.
890 (RT) = gfbmadd(a, (RB), c)
891 # use gfbmadd again since it reduces the result
892 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
895 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
902 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
905 # Instructions for Prime Galois Fields `GF(p)`
907 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
909 ## `gfpadd` Prime Galois Field `GF(p)` Addition
916 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
919 the addition happens on infinite-precision integers
921 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
928 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
931 the subtraction happens on infinite-precision integers
933 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
940 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
943 the multiplication happens on infinite-precision integers
945 ## `gfpinv` Prime Galois Field `GF(p)` Invert
951 Some potential hardware implementations are found in:
952 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
955 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
958 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
961 gfpmadd RT, RA, RB, RC
965 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
968 the multiplication and addition happens on infinite-precision integers
970 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
973 gfpmsub RT, RA, RB, RC
977 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
980 the multiplication and subtraction happens on infinite-precision integers
982 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
985 gfpmsubr RT, RA, RB, RC
989 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
992 the multiplication and subtraction happens on infinite-precision integers
994 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
996 Used in combination with SV FFT REMAP to perform
997 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
998 to avoid the need for a temp register. RS is written
1002 gfpmaddsubr RT, RA, RB, RC
1005 TODO: add link to explanation for where `RS` comes from.
1011 # read all inputs before writing to any outputs in case
1012 # an input overlaps with an output register.
1013 (RT) = gfpmadd(factor1, factor2, term)
1014 (RS) = gfpmsubr(factor1, factor2, term)
1017 # Already in POWER ISA or subsumed
1019 Lists operations either included as part of
1020 other bitmanip operations, or are already in
1025 based on RV bitmanip, covered by ternlog bitops
1028 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1029 return (RA & RB) | (RC & ~RB);
1033 ## count leading/trailing zeros with mask
1039 do i = 0 to 63 if((RB)i=1) then do
1040 if((RS)i=1) then break end end count ← count + 1
1046 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1049 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1050 result = VSR[VRA+32].dword[i].bit[63-k]
1051 VSR[VRT+32].dword[i].bit[63-m] = result
1057 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1060 for (int i = 0, j = 0; i < XLEN; i++)
1061 if ((RB >> i) & 1) {
1063 r |= uint_xlen_t(1) << i;
1073 other way round: identical to RV bext: pextd, found in v3.1 p196
1076 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1079 for (int i = 0, j = 0; i < XLEN; i++)
1080 if ((RB >> i) & 1) {
1082 r |= uint_xlen_t(1) << j;
1091 found in v3.1 p106 so not to be added here
1101 if((RB)63-i==1) then do
1102 result63-ptr1 = (RS)63-i
1108 ## bit to byte permute
1110 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1111 these perform a transpose (bmatflip).
1112 TODO this looks VSX is there a scalar variant
1117 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1118 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1122 superceded by grevlut
1124 based on RV bitmanip, this is also known as a butterfly network. however
1125 where a butterfly network allows setting of every crossbar setting in
1126 every row and every column, generalised-reverse (grev) only allows
1127 a per-row decision: every entry in the same row must either switch or
1130 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1133 uint64_t grev64(uint64_t RA, uint64_t RB)
1136 int shamt = RB & 63;
1137 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1138 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1139 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1140 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1141 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1142 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1143 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1144 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1145 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1146 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1147 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1148 ((x & 0xFFFFFFFF00000000LL) >> 32);
1156 based on RV bitmanip, gorc is superceded by grevlut
1159 uint32_t gorc32(uint32_t RA, uint32_t RB)
1162 int shamt = RB & 31;
1163 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1164 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1165 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1166 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1167 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1170 uint64_t gorc64(uint64_t RA, uint64_t RB)
1173 int shamt = RB & 63;
1174 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1175 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1176 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1177 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1178 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1179 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1180 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1181 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1182 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1183 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1184 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1185 ((x & 0xFFFFFFFF00000000LL) >> 32);
1194 see [[bitmanip/appendix]]