openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
  23
  24 # Code to convert
  25
  26 There are five projects:
  27
  28 * TestIssuer (the HDL)
  29 * ISACaller (the python-based simulator)
  30 * power-gem5 (a cycle accurate simulator)
  31 * Microwatt (VHDL)
  32 * gcc and binutils
  33
  34 Each of these needs to have SV augmentation, and the best way to
  35 do it is if they are all done at the same time, implementing the same
  36 incremental feature.
  37
  38 # Critical tasks
  39
  40 These are prerequisite tasks:
  41
  42 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  43   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  44   just use pygdbmi
  45   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  46 * c++, c and python macros for generating [[sv/svp64]] assembler
  47   (svp64 prefixes)
  48   - python svp64 underway, minimalist sufficient for FU unit tests
  49 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  50 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  51   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  52   - INT and CR EXTRA svp64 fields completed.
  53 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  54
  55 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  56
  57 * Lauri:
  58 * Jacob: C/C++ header for using SV through inline assembly
  59 * Cesar: TestIssuer FSM
  60 * Alain: power-gem5
  61 * Cole:
  62 * Luke: ISACaller, python-assembler-generator-class
  63 * Tobias:
  64 * Alexandre: binutils-svp64-assembler and gcc
  65 * Paul: microwatt
  66
  67 # Adding SV
  68
  69 order: listed in [[sv/overview]]
  70
  71 ## svp64 decoder
  72
  73 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  74
  75 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  76 * power-gem5: TODO
  77 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  78 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  79 * python-based assembler-translator: 40% done (lkcl)
  80 * c++ macros: underway (jacob)
  81
  82 Note when decoding the RM into bits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  83
  84 **IMPORTANT**! when spotting RA=0 in some instructions it is critical to note that the *full **seven** bits* are used (those from EXTRA2/3 included) because RA is no longer only five bits.
  85
  86 Links:
  87
  88 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  89 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  90 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  91
  92 ## SVSTATE SPR needed
  93
  94 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  95
  96 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  97
  98     num name    priv  width
  99     704,SVSTATE,no,no,32
 100     720,SVSRR0,yes,yes,32
 101
 102 Progress:
 103
 104 * ISACaller: done
 105 * power-gem5: TODO
 106 * TestIssuer: TODO
 107 * Microwatt: TODO
 108
 109 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 110
 111 ## Adding SVSTATE "set/get" support for hw/sw debugging
 112
 113 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 114
 115 * LibreSOC DMI/JTAG: TODO
 116 * Microwatt DMI: TODO
 117 * power-gem5 remote gdb: TODO
 118 * TestIssuer: DONE (read-only at least) <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=4d5482810c980ff927ccec62968a40a490ea86eb>
 119
 120 Links:
 121
 122 * <https://bugs.libre-soc.org/show_bug.cgi?id=609>
 123
 124 ## sv.setvl
 125
 126 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 127
 128 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 129 * ISACaller: TODO
 130 * power-gem5: TODO
 131 * TestIssuer: TODO
 132 * Microwatt: TODO
 133
 134 Links:
 135
 136 ## SVSRR0 for exceptions
 137
 138 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 139
 140 * ISACaller: TODO
 141 * power-gem5: TODO
 142 * TestIssuer: TODO
 143 * Microwatt: TODO
 144
 145 ## Illegal instruction exceptions
 146
 147 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 148
 149 * ISACaller: TODO
 150 * power-gem5: TODO
 151 * TestIssuer: TODO
 152 * Microwatt: TODO
 153
 154 ## VL for-loop
 155
 156 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 157
 158 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 159
 160 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 161
 162 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 163
 164 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 165 * power-gem5: TODO
 166 * TestIssuer:
 167   - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 168   - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 169 * Microwatt: TODO
 170
 171 Remember the following register files need to have for-loops, plus
 172 unit tests:
 173
 174 * GPR
 175 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 176 * Condition Registers.  see note below
 177 * FPR (if present)
 178
 179 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 180
 181 ## Increasing register file sizes
 182
 183 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 184
 185 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 186
 187 ## Single Predication
 188
 189 TODO
 190
 191 ## Element width overrides
 192
 193 TODO