openpower/sv/po9_encoding/discussion.mdwn

   1 [[!toc]]
   2
   3 # alternative 32-64 encoding (1)
   4
   5 conflict to resolve: EXT90x and EXT232. they are indistinguishable.
   6
   7 ```
   8 |0-5| 6-27 28 29|30-31|32|33-35|36-37| 38-59 | 60-63 | Description      |
   9 |---|-----|-----|-----|--|-----|-----|-------|-------|------------------|
  10 |PO9| rm0 | 0 0 | 0 0 | 0  000   rm1 |  xxxx | 0000  | SVP64:EXT900     |
  11 |PO9| rm0 | 0 0 | 0 0 | 1  000   rm1 |  xxxx | 0000  | SSingle:EXT900   |
  12 |PO9| xxx | x 0 | 0 0 | x !zero0     |  xxxx | !zero1| 55-bit RESERVED  |
  13 |PO9| xxx | 0 1 | 0 0 |              32-bit EXT900 (Vectorizable)       |
  14 |PO9| xxx | 1 1 | 0 0 |              32-bit EXT901 (Unvectorizable)     |
  15 |PO9|   !ZERO   | 0 0 |  1 | DWi                   | SSingle:EXT232-263 |
  16 |PO9|   0000    | 0 0 |  1 | DWi                   | Scalar EXT232-263  |
  17 |PO9|   RM      | 1 0 |  1 | DWi                   | SVP64:EXT232-263   |
  18 |PO9|   0000    | 0 1 | Defined Word-instruction   | 32-bit Unvec in 64b|
  19 |PO9|   !ZERO   | 0 1 | Defined Word-instruction   | SSingle:EXT000-063 |
  20 |PO9|   RM      | 1 1 | Defined Word-instruction   | SVP64:EXT000-063   |
  21 ```
  22
  23 Fields:
  24
  25 * `RM`: 24-bit SVP64 prefix
  26 * `RM <- rm0 || rm1` split field
  27 * `!zero0 || !zero1` a split field that must not be zero
  28
  29 Length detection:
  30
  31 ```
  32     if PO1                   return 64
  33     elif not PO9             return 32
  34     elif Word[31] = 1        return 64
  35     elif Word[29:30] = 0b10  return 32
  36     elif Word[29:30] = 0b00  return 64
  37     else                     return 32
  38 ```
  39
  40 Instruction allocation restrictions:
  41
  42 * setvl is Unvectorizable but needs more space later: use 55-bit
  43 * likewise svshape svindex and svshape2, all these need 32-bit
  44 * svstep *is* Vectorizable but needs to be encoded 32-bit in order
  45   to reduce loop-size
  46 * space for 32-bit instructions is needed: some instructions
  47   just make no sense if done as 64-bit because they **replace**
  48   two 32-bit instructions.
  49 * but those types of space-saving instructions
  50   **also need to be Vectorizable*
  51
  52 # alternative 32-64 encoding (2)
  53
  54 requires reducing SVP64Single to 23 bits. luckily there are 2 spare
  55
  56 the complexity of attempting to fit 32-bit instructions into
  57 PO9 is very high. encoding (1) attempts to fit `setvl` etc. into
  58 32-bit but it is very tight.  the entire EXT900 area would be
  59 taken up by the SVP64 Management instructions, below, defeating
  60 the purpose of having it.
  61
  62 * `setvl` - Unvectorizable, EXT0xx, `RT RA CTR SVSTATE`, 6-bit XO (including Rc=1)
  63 * `psetvl` - Unvectorizable, EXT1xx, ditto
  64 * `svstep` - Vectorizable, either EXT900 (very precious) or EXT1xx (better), `RT, SVSTATE`, 6-bit XO (including Rc=1)
  65 * `svindex` - Unvectorizable, EXT0xx, `SVSTATE,SVSHAPE0-3`, 5-bit XO
  66 * `psvindex` - Unvectorizable, EXT1xx, ditto
  67 * `svstep(2)` - Unvectorizable, EXT0xx, `SVSTATE,SVSHAPE0-3`, 5-bit XO
  68 * `svstep(2)` - Unvectorizable, EXT1xx, ditto
  69
  70 ```
  71 |0-5| 6-28|29 30 31|32|33-36|37 | 38-60 | 61-63 | Description      |
  72 |---|-----|--------|--|-----|---|-------|-------|------------------|
  73 |PO9| rm0 | 1  0 0 | 0 0000  rm1|  xxxx | 000   | SVP64:EXT900     |
  74 |PO9|!ZERO| 1  0 0 | 0 1000  1  |  xxxx | 000   | SSingle:EXT900   |
  75 |PO9| xxx | 1  0 0 | 0 !zero0   |  xxxx | !zero1| 55-bit RESERVED  |
  76 |PO9| xxx | 0  0 0 |            32-bit EXT900                      |
  77 |PO9|!ZERO| 1  0 0 |  1 | DWi                 | SSingle:EXT232-263 |
  78 |PO9| 000 | 1  0 0 |  1 | DWi                 | Scalar EXT232-263  |
  79 |PO9|  nnnn  | 1 0 |  1 | DWi                 | SVP64:EXT232-263   |
  80 |PO9|  0000  | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b|
  81 |PO9|!ZERO   | 0 1 | Defined Word-instruction | SSingle:EXT000-063 |
  82 |PO9|  nnnn  | 1 1 | Defined Word-instruction | SVP64:EXT000-063   |
  83 ```
  84
  85 Length detection:
  86
  87 ```
  88     if PO1                   return 64
  89     elif not PO9             return 32
  90     elif Word[29:31] = 0b000 return 32
  91     else                     return 64
  92 ```
  93
  94 # alternative 32-64 encoding (3)
  95
  96 TODO
  97 aim of this idea is to attempt simplification of area identification
  98 and length.
  99
 100
 101
 102
 103 ```
 104 |0-5| 6-28|29 30 31|32|33-36|37 | 38-60 | 61-63 | Description      |
 105 |---|-----|--------|--|-----|---|-------|-------|------------------|
 106 |PO9| rm0 | 1  0 0 | 0 0000  rm1|  xxxx | 000   | SVP64:EXT900     |
 107 |PO9|!ZERO| 1  0 0 | 0 1000  1  |  xxxx | 000   | SSingle:EXT900   |
 108 |PO9| xxx | 1  0 0 | 0 !zero0   |  xxxx | !zero1| 55-bit RESERVED  |
 109 |PO9| xxxx   | 0 0 |            32-bit EXT900                      |
 110 |PO9| !ZERO  | 1 0 |  0 | DWi                 | SSingle:EXT232-263 |
 111 |PO9|  0000  | 1 0 |  0 | DWi                 | Scalar EXT232-263  |
 112 |PO9|  nnnn  | 1 0 |  1 | DWi                 | SVP64:EXT232-263   |
 113 |PO9|  0000  | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b|
 114 |PO9| !ZERO  | 0 1 | Defined Word-instruction | SSingle:EXT000-063 |
 115 |PO9|  nnnn  | 1 1 | Defined Word-instruction | SVP64:EXT000-063   |
 116 ```
 117
 118 Length detection:
 119
 120 ```
 121     if PO1                   return 64
 122     elif not PO9             return 32
 123     elif Word[30:31] = 0b00  return 32
 124     else                     return 64
 125 ```
 126
 127 # alternative encoding (3)
 128
 129 derived from <https://bugs.libre-soc.org/show_bug.cgi?id=924#c20>
 130
 131 In order for `Rc` and similar fields to not move for 32-bit instructions, bits
 132 `28:29` are used as the main encoding bits instead of `30:31`.
 133
 134 space saving measures: EXT2xx is half the size
 135
 136 ## length decoding algorithm
 137 ```
 138 if PREFIX[0:5] = 1 then return 64
 139 else if PREFIX[0:5] = 9 then
 140     if PREFIX[28:29] = 3 then
 141         if PREFIX[26:27] = 3 then return 64
 142         else return 32
 143     else return 64
 144 else return 32
 145 ```
 146
 147 ## short table
 148 ```
 149 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 150 | 9| SVRM[0:21]            | 0| 0| SVRM[22:23]| EXT0xx insn    | SVP64 ext0xx
 151 | 9| SVRM[0:21]            | 0| 1| SVRM[22:23]| EXT0xx insn    | SVP64Single ext0xx
 152 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| 0| EXT2xx insn | SVP64 ext2xx
 153 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| 1| EXT2xx insn | SVP64Single ext2xx
 154 | 9| -                 | 00| 1| 1| -          | N/A            | scalar 32-bit
 155 | 9| -                 | 01| 1| 1| -          | N/A            | scalar 32-bit
 156 | 9| -                 | 10| 1| 1| -          | N/A            | scalar 32-bit
 157 | 9| -                 | 11| 1| 1| -                           | scalar 64-bit
 158 | 9| RT| RA| RB| OE| XO| 00| 1| 1| XO     | Rc| N/A            | XO-form 32-bit
 159 | 9| RT| RA| RB| XO    | 00| 1| 1| XO     | Rc| N/A            | X-form 32-bit
 160 | 9| RS| RA| sh| XO    | 00| 1| 1| sh     | Rc| N/A            | XS-form 32-bit
 161 ```
 162
 163 ## SVP64Single in SFFS
 164
 165 important note: SFFS implementations that don't implement SVP64 can still
 166 implement EXT2xx instructions by using the SVP64Single encoding with SVRM=0,
 167 no other SVP64 state needs to be implemented to do that.
 168 (TODO: double check that)
 169
 170 ## full table
 171
 172 note: I mostly stashed stuff in EXT2xx, so the scalar 32-bit space is still
 173 mostly free, most the instructions I wanted in the scalar 32-bit space took
 174 up too much room. I didn't allocate XO values in EXT2xx yet since there's
 175 plenty of space (32 POs equivalent)
 176
 177 note: setvl is split into a 32-bit insn with a common subset of settings and
 178 a full 64-bit insn with all the settings; svstep is 32-bit
 179
 180 note: fmv/fcvt are 32-bit ops, so you can see how they easily fit around bits
 181 26-29 which are used to distinguish from SVP64 prefixes.
 182
 183 ```
 184 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 185 | 9| SVRM[0:21]            | 0| 0| SVRM[22:23]| EXT0xx insn    | SVP64 ext0xx
 186 | 9| SVRM[0:21]            | 0| 1| SVRM[22:23]| EXT0xx insn    | SVP64Single ext0xx
 187 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| 0| EXT2xx insn | SVP64 ext2xx
 188 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| 1| EXT2xx insn | SVP64Single ext2xx
 189 | 9| -                 | 00| 1| 1| -          | N/A            | scalar 32-bit
 190 | 9| -                 | 01| 1| 1| -          | N/A            | scalar 32-bit
 191 | 9| -                 | 10| 1| 1| -          | N/A            | scalar 32-bit
 192 | 9| -                 | 11| 1| 1| -                           | scalar 64-bit
 193 | 9| RT| RA| RB| OE| XO| 00| 1| 1| XO     | Rc| N/A            | XO-form 32-bit
 194 | 9| RT| RA| RB| XO    | 00| 1| 1| XO     | Rc| N/A            | X-form 32-bit
 195 | 9| RS| RA| sh| XO    | 00| 1| 1| sh     | Rc| N/A            | XS-form 32-bit
 196
 197 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 198 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lbzup
 199 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lbzupx
 200 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhzup
 201 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhzupx
 202 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhaup
 203 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhaupx
 204 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwzup
 205 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwzupx
 206 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwaupx
 207 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ldup
 208 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ldupx
 209 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stbup
 210 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stbupx
 211 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthup
 212 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthupx
 213 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwup
 214 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwupx
 215 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stdup
 216 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stdupx
 217 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfdu
 218 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfsup
 219 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfdupx
 220 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lsdupx
 221 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfdup
 222 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfsup
 223 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfdupx
 224 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfsupx
 225 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lbzuspx
 226 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhzuspx
 227 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhauspx
 228 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwzuspx
 229 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwauspx
 230 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lduspx
 231 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stbuspx
 232 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthuspx
 233 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwuspx
 234 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stduspx
 235 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfdupsx
 236 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lsdupsx
 237 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfdupsx
 238 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfsupsx
 239 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lbzsx
 240 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lbzusx
 241 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhzsx
 242 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhzusx
 243 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhasx
 244 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhausx
 245 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwzsx
 246 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwzusx
 247 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwasx
 248 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwausx
 249 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ldsx
 250 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ldusx
 251 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lhbrsx
 252 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lwbrsx
 253 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ldbrsx
 254 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stbsx
 255 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stbusx
 256 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthsx
 257 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthusx
 258 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwsx
 259 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwusx
 260 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stdsx
 261 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stdusx
 262 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | sthbrsx
 263 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stwbrsx
 264 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stdbrsx
 265 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfsxs
 266 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfsuxs
 267 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfdxs
 268 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfduxs
 269 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfiwaxs
 270 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | lfiwzxs
 271 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfsxs
 272 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfsuxs
 273 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfdxs
 274 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfduxs
 275 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | stfiwxs
 276
 277 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 278 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | grevlut
 279 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | grevluti
 280 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ternlogi
 281 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | crternlogi
 282 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | binlut
 283 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | crbinlut
 284
 285 |0 |6  |11  |14        |26 |28|29|30          |32              |
 286 | 9|FRT|mode| XO       | 11| 1| 1| XO         | imm32          | fli 64-bit
 287
 288 |0 |6  |11 |16 |21 |23 |26 |28|29|30      |31 |32|33 |38       |
 289 | 9| RT| RA| RB| sm|000| 00| 1| 1| 0      | Rc| N/A            | shadd
 290 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | shadduw
 291 | 9| RT| RA| RB| sm|000| 00| 1| 1| 1      | Rc| N/A            | shaddw
 292
 293 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 294 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | absdu
 295 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | avgadd
 296 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | minmax
 297 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | absaccs
 298 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | absaccu
 299 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | bmask
 300 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | cprop
 301
 302 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 303 | 9| RT| RA| SVi   |001| 00| 1| 1| vs     | Rc| N/A            | setvl (common 32-bit, ms=vs, vf=0)
 304 | 9| TBD               | 11| 1| 1| TBD                         | setvl (full 64-bit)
 305 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | svremap
 306 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | svshape
 307 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | svshape2
 308 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | svindex
 309 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | mv.swizzle
 310 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fmv.swizzle
 311 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | crrweird
 312 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | mfcrweird
 313 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | mtcrrweird
 314 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | mtcrweird
 315 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | crweirder
 316 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | mcrfm
 317 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fptstp(s)
 318
 319 |0 |6  |11 |13 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 320 | 9| RT| 11|111| SVi   |010| 00| 1| 1| vf     | Rc| N/A            | svstep
 321 | 9| RT| 10|111| FRB   |010| 00| 1| 1| 0      | Rc| N/A            | fmvtg
 322 | 9| RT| 10|111| FRB   |010| 00| 1| 1| 1      | Rc| N/A            | fmvtgs
 323 | 9|FRT| 01|111| RB    |010| 00| 1| 1| 0      | Rc| N/A            | fmvfg
 324 | 9|FRT| 01|111| RB    |010| 00| 1| 1| 1      | Rc| N/A            | fmvfgs
 325 | 9|FRT| IT|110| RB    |010| 00| 1| 1| 0      | Rc| N/A            | fcvtfg
 326 | 9|FRT| IT|110| RB    |010| 00| 1| 1| 1      | Rc| N/A            | fcvtfgs
 327 | 9| RT| IT|CVM| FRB   |010| 00| 1| 1| 0      | Rc| N/A            | fcvttg
 328 | 9|-  | - |0-5| -     |010| 00| 1| 1| 1      | Rc| N/A            | *reserved*
 329
 330 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 331 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | dsld
 332 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | dsrd
 333 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | maddedu
 334 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | maddedus
 335 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | divmod2du
 336
 337 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 338 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffadd(s)
 339 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffsub(s)
 340 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffmul(s)
 341 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffdiv(s)
 342 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fdmadd(s)
 343 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffmadd(s)
 344 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffmsub(s)
 345 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffnmadd(s)
 346 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ffnmsub(s)
 347
 348 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 349 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fsin(s)
 350 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fcos(s)
 351 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ftan(s)
 352 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fasin(s)
 353 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | facos(s)
 354 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fatan(s)
 355 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fsinpi(s)
 356 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fcospi(s)
 357 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ftanpi(s)
 358 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fasinpi(s)
 359 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | facospi(s)
 360 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fatanpi(s)
 361 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fsinh(s)
 362 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fcosh(s)
 363 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | ftanh(s)
 364 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fasinh(s)
 365 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | facosh(s)
 366 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fatanh(s)
 367
 368 |0 |6  |11 |16 |21 |22 |26 |28|29|30      |31 |32|33 |38       |
 369 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | frsqrt(s)
 370 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fcbrt(s)
 371 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | frecip(s)
 372 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexp2m1(s)
 373 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flog2p1(s)
 374 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexp2(s)
 375 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flog2(s)
 376 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexpm1(s)
 377 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flogp1(s)
 378 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexp(s)
 379 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flog(s)
 380 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexp10m1(s)
 381 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flog10p1(s)
 382 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fexp10(s)
 383 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | flog10(s)
 384 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fatan2(s)
 385 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fatan2pi(s)
 386 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fpow(s)
 387 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fpown(s)
 388 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fpowr(s)
 389 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | frootn(s)
 390 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fhypot(s)
 391 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fminmax
 392 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fmod(s)
 393 | 9| SVRM[0:21]            | 1| 0| SVRM[22:23]| -| TBD         | fremainder(s)
 394 ```