openpower/sv/po9_encoding.mdwn

   1 # Definitions
   2
   3 **Proposal: Add the following Definition to Section 1.3.1 of Book I**
   4
   5 Definition of "UnVectoriseable":
   6
   7 Any operation that inherently makes no sense if repeated (through SVP64
   8 Prefixing) is termed "UnVectoriseable" or "UnVectorised".  Examples
   9 include `sc` or `sync` which have no registers. `mtmsr` is also classed
  10 as UnVectoriseable because there is only one `MSR`.
  11
  12 UnVectorised instructions are required to be detected as such if
  13 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
  14 Trap raised.
  15
  16 *Architectural Note: Given that a "pre-classification" Decode Phase is
  17 required (identifying whether the Suffix - Defined Word - is
  18 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
  19 adding "UnVectorised" to this phase is not unreasonable.*
  20
  21 # New 64-bit Instruction Encoding spaces
  22
  23 **Proposal: Add new Section 1.6.5 to Book I**
  24
  25 The following seven new areas are defined within Primary Opcode 9 (EXT009)
  26 as a new 64-bit encoding space, alongside Primary Opcode 1
  27 (EXT1xx).
  28
  29 | 0-5 | 6 | 7 | 8-31  | 32| Description                        |
  30 |-----|---|---|-------|---|------------------------------------|
  31 | PO  | 0 | x | xxxx  | 0 | `RESERVED2` (57-bit) |
  32 | PO  | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
  33 | PO  | 0 | 0 | 0000  | 1 | Scalar EXT232-263               |
  34 | PO  | 0 | 1 | nnnn  | 1 | SVP64:EXT232-263     |
  35 | PO  | 1 | 0 | 0000  | x | `RESERVED1` (32-bit) |
  36 | PO  | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
  37 | PO  | 1 | 1 | nnnn  | n | SVP64:EXT000-063       |
  38
  39 Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
  40 it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
  41 for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
  42 prohibition allows SVP64Single to share its Encoding space with Scalar
  43 Ext232-263 and Scalar EXT300-363.
  44
  45 Also that RESERVED1 and 2 are candidates for future Major opcode
  46 areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas
  47 they may equally be allocated entirely differently.
  48
  49 *Architectural Resource Allocation Note: **under no circumstances** must
  50 different Defined Words be allocated within any `EXT{z}` prefixed or
  51 unprefixed space for a given value of `z` of 0, 2 or 3. Even if UnVectoriseable
  52 an instruction Defined Word space must have the exact same Instruction
  53 and exact same Instruction Encoding in all spaces being RESERVED (Illegal
  54 Instruction Trap if UnVectoriseable) or not be allocated at all.
  55 This is required as an inviolate hard rule governing Primary Opcode 9
  56 that may not be revoked under any circumstances. A useful way to think
  57 of this is that the Prefix Encoding is, like the 8086 REP instruction,
  58 an independent 32-bit Defined Word. The only semi-exceptions are
  59 the Post-Increment Mode of LD/ST-Update and Vectorised Branch-Conditional.*
  60
  61 Encoding spaces and their potential are illustrated:
  62
  63 | Encoding |Available bits|Scalar|Vectoriseable | SVP64Single  | PO1-Prefixable |
  64 |----------|--------------|------|--------------|--------------|----------------|
  65 |EXT000-063| 32           | yes  | yes          |yes           |yes             |
  66 |EXT100-163| 64           | yes  | no           |no            |not twice       |
  67 |RESERVED2 | 57           | N/A  |not applicable|not applicable|not applicable  |
  68 |EXT232-263| 32           | yes  | yes          |yes           |no              |
  69 |RESERVED1 | 32           | N/A  | no           |no            |no              |
  70
  71 Notes:
  72
  73 * Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
  74   thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit
  75   on top of an SVP64 prefix which is 32-bit on top of a Defined Word
  76   and the complexity at the Decoder becomes too great for High
  77   Performance Multi-Issue systems.
  78 * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being
  79   double-PO1-prefixed (not twice prefixed)
  80 * RESERVED2 presently remains unallocated as of yet and therefore its
  81   potential is not yet defined (Not Applicable).
  82 * RESERVED1 is also unallocated at present, but it is known in advance
  83   that the area is UnVectoriseable and also cannot be Prefixed with
  84   SVP64Single.
  85 * Considerable care is needed both on Architectural Resource Allocation
  86   as well as instruction design itself.  Once an instruction is allocated
  87   in an UnVectoriseable area it can never be Vectorised without providing
  88   an entirely new Encoding.
  89
  90 [[!tag standards]]
  91
  92 --------
  93
  94 \newpage{}
  95