openpower/sv/rfc/ls004.mdwn

   1 # RFC ls004  Shift-And-Add
   2
   3 **URLs**:
   4
   5 * <https://libre-soc.org/openpower/sv/biginteger/analysis/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls004/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=960>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/91>
   9 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
  10
  11 **Severity**: Major
  12
  13 **Status**: New
  14
  15 **Date**: 31 Oct 2022
  16
  17 **Target**: v3.2B
  18
  19 **Source**: v3.0B
  20
  21 **Books and Section affected**:
  22
  23 ```
  24     Book I Fixed-Point Shift Instructions 3.3.14.2
  25     Appendix E Power ISA sorted by opcode
  26     Appendix F Power ISA sorted by version
  27     Appendix G Power ISA sorted by Compliancy Subset
  28     Appendix H Power ISA sorted by mnemonic
  29 ```
  30
  31 **Summary**
  32
  33 ```
  34     Instructions added
  35     shadd - Shift and Add
  36     shadduw - Shift and Add Unsigned Word
  37 ```
  38
  39 **Submitter**: Luke Leighton (Libre-SOC)
  40
  41 **Requester**: Libre-SOC
  42
  43 **Impact on processor**:
  44
  45 ```
  46     Addition of two new GPR-based instructions
  47 ```
  48
  49 **Impact on software**:
  50
  51 ```
  52     Requires support for new instructions in assembler, debuggers,
  53     and related tools.
  54 ```
  55
  56 **Keywords**:
  57
  58 ```
  59     GPR, Big-manip, Shift, Arithmetic
  60 ```
  61
  62 **Motivation**
  63
  64 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
  65 Adding more LD/ST is too complex, a compromise is to add shift-and-add.
  66 Replaces a pair of explicit instructions in hot-loops.
  67
  68 **Notes and Observations**:
  69
  70 1. `shadd` and `shadduw` operate on unsigned integers.
  71 2. `shadduw` masks the upper 32-bits of the operand to-be-shifted.
  72 3. These are both 2-in 1-out instructions.
  73
  74 **Changes**
  75
  76 Add the following entries to:
  77
  78 * the Appendices of Book I
  79 * Instructions of Book I added to Section 3.3.14.2
  80
  81 ----------------
  82
  83 \newpage{}
  84
  85 # Shift-and-Add
  86
  87 `shadd RT, RA, RB`
  88
  89 |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
  90 |-------|------|-------|-------|-------|-------|----|----------|
  91 |  PO   | RT   |  RA   |  RB   |  sm   |  XO   | Rc | Z23-Form |
  92
  93 Pseudocode:
  94
  95     shift <- sm + 1                                 # Shift is between 1-4
  96     sum[0:63] <- ((RB) << shift) + (RA) # Shift RB, add RA
  97     RT <- sum                                       # Result stored in RT
  98
  99 `shift` is determined by the 2-bit bitfield `sm`+1.
 100 The minimum shift as 1, maximum 4.
 101 The result is shifted (RB) + (RA), and is stored in register RT.
 102
 103 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 104
 105 **NEED EXAMPLES (not sure how to embedd sm)!!!**
 106 Examples:
 107 ```
 108 #
 109 shadd r4, r1, r2
 110 ```
 111
 112 # Shift-and-Add Upper Word
 113
 114 `shadd RT, RA, RB`
 115
 116 |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
 117 |-------|------|-------|-------|-------|-------|----|----------|
 118 |  PO   | RT   |  RA   |  RB   |  sm   |  XO   | Rc | Z23-Form |
 119
 120 Pseudocode:
 121
 122     shift <- shift + 1                          # Shift is between 1-4
 123     n <- (RB)[XLEN/2:XLEN-1]                # Limit RB to upper word (32-bits)
 124     sum[0:63] <- (n << shift) + (RA)    # Shift n, add RA
 125     RT <- sum                                       # Result stored in RT
 126
 127 `shift` is determined by the 2-bit bitfield `sm`+1.
 128 Mask (RB) to only use the upper word (32-bits).
 129 The minimum shift as 1, maximum 4.
 130 The result is shifted `n` + (RA), and is stored in register RT.
 131
 132 Operands RA and RB, and the result RT are all 64-bit, unsigned integers.
 133
 134 Examples:
 135 ```
 136 #
 137 shadduw r4, r1, r2
 138 ```
 139
 140
 141 [[!tag opf_rfc]]
 142
 143 # Appendices
 144
 145     Appendix E Power ISA sorted by opcode
 146     Appendix F Power ISA sorted by version
 147     Appendix G Power ISA sorted by Compliancy Subset
 148     Appendix H Power ISA sorted by mnemonic
 149
 150 | Form | Book | Page | Version | mnemonic | Description |
 151 |------|------|------|---------|----------|-------------|
 152 | Z23  | I    | #    | 3.0B    | shadd    | Shift-and-Add |
 153 | Z23  | I    | #    | 3.0B    | shadduw  | Shift-and-Add Unsigned Word |
 154