mention SVP64 in ls005
[libreriscv.git] / openpower / sv / rfc / ls005.mdwn
1 # OPF ISA WG External RFC ls005 v1: XLEN
2
3 * RFC Author: Luke Kenneth Casson Leighton.
4 * RFC Contributors/Ideas: Jacob Lifshay, Toshaan Bharvani
5 * Funded by NLnet under the NGI Zero Entrust EU Horizon Europe Grant 101069594
6
7 **URLs**:
8
9 * <https://libre-soc.org/openpower/sv/rfc/ls005/>
10 * <https://bugs.libre-soc.org/show_bug.cgi?id=671>
11 * <https://bugs.libre-soc.org/show_bug.cgi?id=663>
12 * <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD>
13 * <https://git.openpower.foundation/isa/PowerISA/issues/104>
14
15 **Severity**: Major
16
17 **Status**: New
18
19 **Date**: 22 Dec 2022
20
21 **Target**: v3.2B
22
23 **Source**: v3.0B
24
25 **Books and Section affected**:
26
27 ```
28 Everything (in a consistent, regular and systematic fashion)
29 ```
30
31 **Summary**
32
33 ```
34 Exactly as is already done in RISC-V, convert the entire
35 use of 64-bit hard-coding to "XLEN". Exactly as is in RISC-V,
36 options then include PowerISA-32, PowerISA-64 and PowerISA-128.
37 Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is
38 also floated, for Embedded, AI, Edge, Processing-in-Memory,
39 Distributed Computing and other purposes.
40 ```
41
42 **Submitter**: Luke Leighton (Libre-SOC)
43
44 **Requester**: Libre-SOC
45
46 **Impact on processor**:
47
48 ```
49 Entirely new processors, entirely new markets.
50 ```
51
52 **Impact on software**:
53
54 ```
55 Massive but regular, consistent, and systematic.
56 ```
57
58 **Keywords**:
59
60 ```
61 XLEN
62 ```
63
64 **Motivation**
65
66 The Power ISA is far too massive, making it wholly unsuited for Embedded
67 markets and adversely impacting its reach and potential. The RISC paradigm
68 it is based on has gone too far into PackedSIMD (128-bit). Fixing this is
69 relatively and conceptually straightforward: allow 32-bit and even 16-bit
70 and 8-bit implementations, and use the opportunity to allow future Scalar
71 128-bit implementations in the exact same strategic way that RISC-V has RV128.
72
73 Register files are redefined to XLEN width but are permitted to "group"
74 registers together to create 16-bit, 32-bit and 64-bit addresses.
75 In this way, the limitations of what would otherwise restrict the usefulness
76 of a severely-targetted application-specific processor may be overcome in
77 order to make it still possible to (at reduced performance) still run
78 general-purpose applications.
79
80 AI application-specific processing or other Processing-In-Memory or other
81 specialist design therefore may for example focus a balance
82 of raw computing power heavily onto 8-bit or 16-bit computation, but still
83 gain the benefit of the Power ISA and everything it brings. Contrast
84 this with the more "normal" approach of creating heavily-focussed
85 specialist "AI" Engines incapable of Turing-completeness and the benefits
86 are clear.
87
88 Note: SVP64 **requires** this change as a 100% critical dependency.
89 SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
90 64-bit), read from, processed, and returned to, the standard **Scalar**
91 Register Files, with byte-level write-enable lines.
92
93 **Changes**
94
95 For all pseudocode right across the board in all Scalar operations, replace
96 hard-coded "64" with "XLEN". **This work is already underway as sponsored
97 by NLnet in the Libre-SOC Power ISA Pseudocode**. The default is obviously
98 recommended to be "XLEN=64" in order to create zero disruption.
99
100 Definitions of the Register File(s) for GPR and FPR are then changed to be
101 "XLEN" wide. However, for Embedded purposes (XLEN=32/16/8), an SPR controls
102 whether (and how many) sequentially-grouped registers are taken together to
103 create 16-bit, 32-bit and 64-bit addresses (depending on application need).
104
105 ----------------
106
107 \newpage{}
108