openpower/sv/rfc/ls008.mdwn

   1 # RFC ls008 SVP64 Management instructions
   2
   3 [[!tag opf_rfc]]
   4
   5 **URLs**:
   6
   7 * <https://libre-soc.org/openpower/sv/>
   8 * <https://libre-soc.org/openpower/sv/rfc/ls008/>
   9 * <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
  10 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
  11
  12 **Severity**: Major
  13
  14 **Status**: New
  15
  16 **Date**: 24 Mar 2023
  17
  18 **Target**: v3.2B
  19
  20 **Source**: v3.0B
  21
  22 **Books and Section affected**:
  23
  24 ```
  25     Book I, new Scalar Chapter.  (Or, new Book on "Zero-Overhead Loop Subsystem")
  26     Appendix E Power ISA sorted by opcode
  27     Appendix F Power ISA sorted by version
  28     Appendix G Power ISA sorted by Compliancy Subset
  29     Appendix H Power ISA sorted by mnemonic
  30 ```
  31
  32 **Summary**
  33
  34 ```
  35     Instructions added
  36     setvl    - Cray-style "Set Vector Length" instruction
  37     svstep   - Vertical-First Mode explicit Step and Status
  38     svremap  - Re-Mapping of Register Element Offsets
  39     svindex  - General-purpose setting of SHAPEs to be re-mapped
  40     svshape  - Hardware-level setting of SHAPEs for element re-mapping
  41     svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
  42 ```
  43
  44 **Submitter**: Luke Leighton (Libre-SOC)
  45
  46 **Requester**: Libre-SOC
  47
  48 **Impact on processor**:
  49
  50 ```
  51     Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  52     Management Instructions which can be implemented extremely efficiently
  53     and effectively by inserting an additional phase between Decode and Issue.
  54     More complex designs are NOT adversely impacted and in fact greatly benefit
  55     whilst still retaining an obvious linear sequential execution programming model.
  56 ```
  57
  58 **Impact on software**:
  59
  60 ```
  61     Requires support for new instructions in assembler, debuggers,
  62     and related tools.
  63 ```
  64
  65 **Keywords**:
  66
  67 ```
  68     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control,
  69     Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model
  70 ```
  71
  72 **Motivation**
  73
  74 TODO
  75
  76 **Notes and Observations**:
  77
  78 1. TODO
  79
  80 **Changes**
  81
  82 Add the following entries to:
  83
  84 * the Appendices of Book I
  85 * Instructions of Book I as a new Section
  86 * SVL-Form of Book I Section 1.6.1.6 and 1.6.2
  87
  88 ----------------
  89
  90 \newpage{}
  91
  92 # svstep: Vertical-First Stepping and status reporting
  93
  94 SVL-Form
  95
  96 * svstep RT,SVi,vf (Rc=0)
  97 * svstep. RT,SVi,vf (Rc=1)
  98
  99 | 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
 100 |----|----|-----|------|----------|-------|--|--------- |
 101 |PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |
 102
 103 Pseudo-code:
 104
 105 ```
 106     if SVi[3:4] = 0b11 then
 107         # store subvl, pack and unpack in SVSTATE
 108         SVSTATE[53] <- SVi[5]
 109         SVSTATE[54] <- SVi[6]
 110         RT <- [0]*62 || SVSTATE[53:54]
 111     else
 112         step <- SVSTATE_NEXT(SVi, vf)
 113         RT <- [0]*57 || step
 114
 115 ```
 116
 117 Special Registers Altered:
 118
 119     CR0                     (if Rc=1)
 120
 121
 122 -------------
 123
 124 \newpage{}
 125
 126 # SVL-Form
 127
 128 Add the following to Book I, 1.6.1, SVL-Form
 129
 130 ```
 131     |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 132     | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
 133     | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
 134 ```
 135
 136 * Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
 137 * Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
 138 * Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
 139 * Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
 140
 141 Add the following to Book I, 1.6.2
 142
 143 ```
 144
 145 ```
 146
 147
 148 # Appendices
 149
 150     Appendix E Power ISA sorted by opcode
 151     Appendix F Power ISA sorted by version
 152     Appendix G Power ISA sorted by Compliancy Subset
 153     Appendix H Power ISA sorted by mnemonic
 154
 155 | Form | Book | Page | Version | mnemonic | Description |
 156 |------|------|------|---------|----------|-------------|
 157 | SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status reporting |
 158