openpower/sv/rfc/ls009.mdwn

   1 # RFC ls009 SVP64 REMAP instructions
   2
   3 **URLs**:
   4
   5 * <https://libre-soc.org/openpower/sv/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls009/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 24 Mar 2023
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.0B
  19
  20 **Books and Section affected**:
  21
  22 ```
  23     Book I, new Zero-Overhead-Loop Chapter.
  24     Appendix E Power ISA sorted by opcode
  25     Appendix F Power ISA sorted by version
  26     Appendix G Power ISA sorted by Compliancy Subset
  27     Appendix H Power ISA sorted by mnemonic
  28 ```
  29
  30 **Summary**
  31
  32 ```
  33     svremap  - Re-Mapping of Register Element Offsets
  34     svindex  - General-purpose setting of SHAPEs to be re-mapped
  35     svshape  - Hardware-level setting of SHAPEs for element re-mapping
  36     svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
  37 ```
  38
  39 **Submitter**: Luke Leighton (Libre-SOC)
  40
  41 **Requester**: Libre-SOC
  42
  43 **Impact on processor**:
  44
  45 ```
  46     Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  47     Management Instructions which provide advanced features such as Matrix
  48     FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
  49 ```
  50
  51 **Impact on software**:
  52
  53 ```
  54     Requires support for new instructions in assembler, debuggers,
  55     and related tools.
  56 ```
  57
  58 **Keywords**:
  59
  60 ```
  61     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
  62     Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  63     Digital Signal Processing (DSP)
  64 ```
  65
  66 **Motivation**
  67
  68 These REMAP Management instructions provide state-of-the-art advanced capabilities
  69 to dramatically decrease instruction count and power reduction whilst retaining
  70 unprecedented general-purpose capability and a standard Sequential Execution Model.
  71
  72 **Notes and Observations**:
  73
  74 1. TODO
  75
  76 **Changes**
  77
  78 Add the following entries to:
  79
  80 * the Appendices of Book I
  81 * Instructions of Book I as a new Section
  82 * TODO-Form of Book I Section 1.6.1.6 and 1.6.2
  83
  84 ----------------
  85
  86 \newpage{}
  87
  88 # svstep: Vertical-First Stepping and status reporting
  89
  90 SVL-Form
  91
  92 * svstep RT,SVi,vf (Rc=0)
  93 * svstep. RT,SVi,vf (Rc=1)
  94
  95 | 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
  96 |----|----|-----|------|----------|-------|--|--------- |
  97 |PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |
  98
  99 Pseudo-code:
 100
 101 ```
 102     if SVi[3:4] = 0b11 then
 103         # store pack and unpack in SVSTATE
 104         SVSTATE[53] <- SVi[5]
 105         SVSTATE[54] <- SVi[6]
 106         RT <- [0]*62 || SVSTATE[53:54]
 107     else
 108         # Vertical-First explicit stepping.
 109         step <- SVSTATE_NEXT(SVi, vf)
 110         RT <- [0]*57 || step
 111 ```
 112
 113 Special Registers Altered:
 114
 115     CR0                     (if Rc=1)
 116
 117 **Description**
 118
 119
 120 -------------
 121
 122 \newpage{}
 123
 124
 125 -------------
 126
 127 \newpage{}
 128
 129 # Forms
 130
 131 Add the following to Book I, 1.6.1, SVI-Form
 132
 133 ```
 134     |0     |6    |11    |16   |21 |23  |24|25|26    31|
 135     | PO   |  SVG|rmm   | SVd |ew |SVyx|mm|sk|   XO   |
 136 ```
 137
 138 Add the following to Book I, 1.6.1, SVM-Form
 139
 140 ```
 141     |0     |6        |11      |16    |21    |25 |26    |31  |
 142     | PO   |  SVxd   |   SVyd | SVzd | SVrm |vf |   XO      |
 143 ```
 144
 145 Add the following to Book I, 1.6.1, SVM2-Form
 146
 147 ```
 148 # 1.6.35.1 SVM2-FORM
 149     |0     |6     |10  |11      |16    |21 |24|25 |26    |31  |
 150     | PO   | SVo  |SVyx|   rmm  | SVd  |XO |mm|sk |   XO      |
 151 ```
 152
 153 Add the following to Book I, 1.6.1, SVRM-Form
 154
 155 ```
 156 # 1.6.36 SVRM-FORM
 157     |0     |6     |11  |13   |15   |17   |19   |21  |22   |26     |31 |
 158     | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO        |
 159 ```
 160
 161 * Add `SVI, SVM, SVM2, SVRM` to `XO (26:31)` Field in Book I, 1.6.2
 162
 163 Add the following to Book I, 1.6.2
 164
 165 ```
 166     mi0 (11:12)
 167         Field used in REMAP to select the SVSHAPE for 1st input register
 168         Formats: SVRM
 169     mi1 (13:14)
 170         Field used in REMAP to select the SVSHAPE for 2nd input register
 171         Formats: SVRM
 172     mi2 (15:16)
 173         Field used in REMAP to select the SVSHAPE for 3rd input register
 174         Formats: SVRM
 175     mm (24)
 176         Field used to specify the meaning of the rmm field for SVI-Form
 177         and SVM2-Form
 178         Formats: SVI, SVM2
 179     mo0 (17:18)
 180         Field used in REMAP to select the SVSHAPE for 1st output register
 181         Formats: SVRM
 182     mo1 (19:20)
 183         Field used in REMAP to select the SVSHAPE for 2nd output register
 184         Formats: SVRM
 185     pst (21)
 186         Field used in REMAP to indicate "persistence" mode (REMAP
 187         continues to apply to multiple instructions)
 188         Formats: SVRM
 189     rmm (11:15)
 190         REMAP Mode field for SVI-Form and SVM2-Form
 191         Formats: SVI, SVM2
 192     sk (25)
 193         Field used to specify dimensional skipping in svindex
 194         Formats: SVI, SVM2
 195     SVd (16:20)
 196         Immediate field used to specify the size of the REMAP dimension
 197         in the svindex and svshape2 instructions
 198         Formats: SVI, SVM2
 199     SVDS (16:29)
 200         Immediate field used to specify a 9-bit signed
 201         two's complement integer which is concatenated
 202         on the right with 0b00 and sign-extended to 64 bits.
 203         Formats: SVDS
 204     SVG (6:10)
 205         Field used to specify a GPR to be used as a
 206         source for indexing.
 207         Formats: SVI
 208     SVi (16:22)
 209          Simple-V immediate field for setting VL or MVL
 210          Formats: SVL
 211     SVme (6:10)
 212          Simple-V "REMAP" map-enable bits (0-4)
 213          Formats: SVRM
 214     SVo (6:9)
 215         Field used by the svshape2 instruction as an offset
 216         Formats: SVM2
 217     SVrm (21:24)
 218          Simple-V "REMAP" Mode
 219          Formats: SVM
 220     SVxd (6:10)
 221          Simple-V "REMAP" x-dimension size
 222          Formats: SVM
 223     SVyd (11:15)
 224          Simple-V "REMAP" y-dimension size
 225          Formats: SVM
 226     SVzd (16:20)
 227          Simple-V "REMAP" z-dimension size
 228          Formats: SVM
 229 ```
 230
 231 # Appendices
 232
 233     Appendix E Power ISA sorted by opcode
 234     Appendix F Power ISA sorted by version
 235     Appendix G Power ISA sorted by Compliancy Subset
 236     Appendix H Power ISA sorted by mnemonic
 237
 238 | Form | Book | Page | Version | mnemonic | Description |
 239 |------|------|------|---------|----------|-------------|
 240 | SVRM | I    | #    | 3.0B    | svremap    | REMAP enabling instruction |
 241
 242 [[!tag opf_rfc]]