openpower/sv/rfc/ls009.mdwn

   1 # RFC ls009 SVP64 REMAP instructions
   2
   3 **URLs**:
   4
   5 * <https://libre-soc.org/openpower/sv/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls009/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 24 Mar 2023
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.0B
  19
  20 **Books and Section affected**:
  21
  22 ```
  23     Book I, new Zero-Overhead-Loop Chapter.
  24     Appendix E Power ISA sorted by opcode
  25     Appendix F Power ISA sorted by version
  26     Appendix G Power ISA sorted by Compliancy Subset
  27     Appendix H Power ISA sorted by mnemonic
  28 ```
  29
  30 **Summary**
  31
  32 ```
  33     svremap  - Re-Mapping of Register Element Offsets
  34     svindex  - General-purpose setting of SHAPEs to be re-mapped
  35     svshape  - Hardware-level setting of SHAPEs for element re-mapping
  36     svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
  37 ```
  38
  39 **Submitter**: Luke Leighton (Libre-SOC)
  40
  41 **Requester**: Libre-SOC
  42
  43 **Impact on processor**:
  44
  45 ```
  46     Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  47     Management Instructions which provide advanced features such as Matrix
  48     FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
  49 ```
  50
  51 **Impact on software**:
  52
  53 ```
  54     Requires support for new instructions in assembler, debuggers,
  55     and related tools.
  56 ```
  57
  58 **Keywords**:
  59
  60 ```
  61     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
  62     Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  63     Digital Signal Processing (DSP)
  64 ```
  65
  66 **Motivation**
  67
  68 These REMAP Management instructions provide state-of-the-art advanced capabilities
  69 to dramatically decrease instruction count and power reduction whilst retaining
  70 unprecedented general-purpose capability and a standard Sequential Execution Model.
  71
  72 **Notes and Observations**:
  73
  74 1. TODO
  75
  76 **Changes**
  77
  78 Add the following entries to:
  79
  80 * the Appendices of Book I
  81 * Instructions of Book I as a new Section
  82 * TODO-Form of Book I Section 1.6.1.6 and 1.6.2
  83
  84 ----------------
  85
  86 \newpage{}
  87
  88 # svstep: Vertical-First Stepping and status reporting
  89
  90 SVL-Form
  91
  92 * svstep RT,SVi,vf (Rc=0)
  93 * svstep. RT,SVi,vf (Rc=1)
  94
  95 | 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
  96 |----|----|-----|------|----------|-------|--|--------- |
  97 |PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |
  98
  99 Pseudo-code:
 100
 101 ```
 102     if SVi[3:4] = 0b11 then
 103         # store pack and unpack in SVSTATE
 104         SVSTATE[53] <- SVi[5]
 105         SVSTATE[54] <- SVi[6]
 106         RT <- [0]*62 || SVSTATE[53:54]
 107     else
 108         # Vertical-First explicit stepping.
 109         step <- SVSTATE_NEXT(SVi, vf)
 110         RT <- [0]*57 || step
 111 ```
 112
 113 Special Registers Altered:
 114
 115     CR0                     (if Rc=1)
 116
 117 **Description**
 118
 119
 120 -------------
 121
 122 \newpage{}
 123
 124
 125 -------------
 126
 127 \newpage{}
 128
 129 # SVL-Form
 130
 131 Add the following to Book I, 1.6.1, SVL-Form
 132
 133 ```
 134     |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 135     | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
 136     | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
 137 ```
 138
 139 * Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
 140 * Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
 141 * Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
 142 * Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
 143
 144 Add the following to Book I, 1.6.2
 145
 146 ```
 147     ms (23)
 148         Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
 149         is to be set
 150         Formats: SVL
 151     vf (25)
 152         Field used in Simple-V to specify whether "Vertical" Mode is set
 153         (vfirst in the SVSTATE SPR)
 154         Formats: SVL
 155     vs (24)
 156         Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
 157         Formats: SVL
 158     SVi (16:22)
 159          Simple-V immediate field used by setvl for setting VL or MVL
 160          (vl, maxvl in the SVSTATE SPR)
 161          and used as a "Mode of Operation" selector in svstep
 162          Formats: SVL
 163 ```
 164
 165 # Appendices
 166
 167     Appendix E Power ISA sorted by opcode
 168     Appendix F Power ISA sorted by version
 169     Appendix G Power ISA sorted by Compliancy Subset
 170     Appendix H Power ISA sorted by mnemonic
 171
 172 | Form | Book | Page | Version | mnemonic | Description |
 173 |------|------|------|---------|----------|-------------|
 174 | SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status reporting |
 175 | SVL  | I    | #    | 3.0B    | setvl    | Cray-like establishment of Looping (Vector) context |
 176
 177 [[!tag opf_rfc]]