1 # RFC ls009 SVP64 Zero-Overhead Loop Prefix Subsystem
3 Credits and acknowledgements:
11 * NLnet Foundation, for funding
12 * OpenPOWER Foundation
15 * IBM for the Power ISA itself
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
23 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section.
24 It is also crucial to note that whilst this format augments instruction
25 behaviour it works in conjunction with SVSTATE and other [[sv/sprs]].
27 Except where explicitly stated all bit numbers remain as in the Power ISA:
28 in MSB0 form (the bits are numbered from 0 at the MSB on the left
29 and counting up as you move rightwards to the LSB end). All bit ranges are inclusive
30 (so `4:6` means bits 4, 5, and 6, in MSB0 order). **All register numbering and
31 element numbering however is LSB0 ordering** which is a different convention used
32 elsewhere in the Power ISA.
34 64-bit instructions are split into two 32-bit words, the prefix and the
35 suffix. The prefix always comes before the suffix in PC order.
37 | 0:5 | 6:31 | 32:63 |
38 |--------|--------------|--------------|
39 | EXT01 | v3.1 Prefix | v3.0/1 Suffix |
41 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
43 Subset implementations in hardware are permitted, as long as certain
44 rules are followed, allowing for full soft-emulation including future
45 revisions. Compliancy Subsets exist to ensure minimum levels of binary
46 interoperability expectations within certain environments.
48 ## Register files, elements, and Element-width Overrides
50 In the Upper Compliancy Levels the size of the GPR and FPR Register files are expanded
51 from 32 to 128 entries, and the number of CR Fields expanded from CR0-CR7 to CR0-CR127.
53 Memory access remains exactly the same: the effects of `MSR.LE` remain exactly the same,
54 affecting as they already do and remain to **only** the Load and Store memory-register
55 operation byte-order, and having nothing to do with the
56 ordering of the contents of register files or register-register operations.
58 Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered and for
59 numbering to be sequentially incremental the element offset numbering is naturally
60 **LSB0-sequentially-incrementing from zero not MSB0-incrementing.** Expressed exclusively in
61 MSB0-numbering, SVP64 is unnecessarily complex to understand: the required
62 subtractions from 63, 31, 15 and 7 unfortunately become a hostile minefield.
63 Therefore for the purposes of this section the more natural
64 **LSB0 numbering is assumed** and it is up to the reader to translate to MSB0 numbering.
66 The Canonical specification for how element-sequential numbering and element-width
67 overrides is defined is expressed in the following c structure, assuming a Little-Endian
68 system, and naturally using LSB0 numbering everywhere because the ANSI c specification
74 uint8_t b[]; // elwidth 8
75 uint16_t s[]; // elwidth 16
76 uint32_t i[]; // elwidth 32
77 uint64_t l[]; // elwidth 64
78 uint8_t actual_bytes[8];
81 elreg_t int_regfile[128];
83 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
85 case 64: el->l = int_regfile[gpr].l[element];
90 Example add operation implementation when elwidths are 64-bit:
93 # add RT, RA,RB using the "uint64_t" union member, "l"
95 int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
98 However if elwidth overrides are set to 16 for both source and destination:
101 # add RT, RA, RB using the "uint64_t" union member "s"
103 int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
106 Hardware Architectural note: to avoid a Read-Modify-Write at the register file it is
107 strongly recommended to implement byte-level write-enable lines exactly as has been
108 implemented in DRAM ICs for many decades. Additionally the predicate mask bit is advised
109 to be associated with the element operation and ultimately passed to the register file.
110 When element-width is set to 64-bit the relevant predicate mask bit may be repeated
111 eight times and pull all eight write-port byte-level lines HIGH. Clearly when element-width
112 is set to 8-bit the relevant predicate mask bit corresponds directly with one single
113 byte-level write-enable line. It is up to the Hardware Architect to then amortise (merge)
114 elements together into both PredicatedSIMD Pipelines as well as simultaneous non-overlapping
115 Register File writesto achieve High Performance designs.
117 ## SVP64 encoding features
119 A number of features need to be compacted into a very small space of only 24 bits:
121 * Independent per-register Scalar/Vector tagging and range extension on every register
122 * Element width overrides on both source and destination
123 * Predication on both source and destination
124 * Two different sources of predication: INT and CR Fields
125 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
126 predicate-result mode.
128 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
130 # Definition of Reserved in this spec.
132 For the new fields added in SVP64, instructions that have any of their
133 fields set to a reserved value must cause an illegal instruction trap,
134 to allow emulation of future instruction sets, or for subsets of SVP64
135 to be implemented in hardware and the rest emulated.
136 This includes SVP64 SPRs: reading or writing values which are not
137 supported in hardware must also raise illegal instruction traps
138 in order to allow emulation.
139 Unless otherwise stated, reserved values are always all zeros.
141 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard Power ISA definition
142 is intended the red keyword `RESERVED` is used.
144 # Scalar Identity Behaviour
146 SVP64 is designed so that when the prefix is all zeros, and
148 influence occurs (no augmentation) such that all standard Power ISA
149 v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
151 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
152 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
154 # Register Naming and size
156 SV Registers are simply the INT, FP and CR register files extended
157 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
159 Where the integer regfile in standard scalar
160 Power ISA v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
161 Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields
163 extended to 128 entries, CR0 thru CR127.
165 The names of the registers therefore reflects a simple linear extension
166 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
167 would be reflected by a linear increase in the size of the underlying
168 SRAM used for the regfiles.
170 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
171 so that the register fields are identical to as if SV was not in effect
172 i.e. under these circumstances (EXTRA=0) the register field names RA,
173 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
174 `scalar identity behaviour` described above.
178 With the way that EXTRA fields are defined and applied to register fields,
179 future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Further discussion is out of scope for this version of SVP64.
181 # Remapped Encoding (`RM[0:23]`)
183 To allow relatively easy remapping of which portions of the Prefix Opcode
184 Map are used for SVP64 without needing to rewrite a large portion of the
185 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
186 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
189 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
190 is defined in the Prefix Fields section.
192 ## Prefix Opcode Map (64-bit instruction encoding)
194 In the original table in the v3.1B Power ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
196 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
197 empty spaces are yet-to-be-allocated Illegal Instructions.
199 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
200 |------|--------|--------|--------|--------|--------|--------|--------|--------|
201 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
202 |001---| | | | | | | | |
203 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
204 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
205 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
206 |101---| | | | | | | | |
207 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
208 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
210 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
214 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
215 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
216 This is achieved by setting bits 7 and 9 to 1:
218 | Name | Bits | Value | Description |
219 |------------|---------|-------|--------------------------------|
220 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
221 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
222 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
223 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
224 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
225 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
227 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
230 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
231 |--------|-------|---|-------|---|----------|
232 | EXT01 | RM | 1 | RM | 1 | RM |
233 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
235 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
236 instruction. That instruction becomes "prefixed" with the SVP context: the
237 Remapped Encoding field (RM).
239 It is important to note that unlike v3.1 64-bit prefixed instructions
240 there is insufficient space in `RM` to provide identification of
241 any SVP64 Fields without first partially decoding the
242 32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
243 `RM` format is individually associated with every instruction.
245 Extreme caution and care must therefore be taken
246 when extending SVP64 in future, to not create unnecessary relationships
247 between prefix and suffix that could complicate decoding, adding latency.
251 The following fields are common to all Remapped Encodings:
253 | Field Name | Field bits | Description |
254 |------------|------------|----------------------------------------|
255 | MASKMODE | `0` | Execution (predication) Mask Kind |
256 | MASK | `1:3` | Execution Mask |
257 | SUBVL | `8:9` | Sub-vector length |
259 The following fields are optional or encoded differently depending
260 on context after decoding of the Scalar suffix:
262 | Field Name | Field bits | Description |
263 |------------|------------|----------------------------------------|
264 | ELWIDTH | `4:5` | Element Width |
265 | ELWIDTH_SRC | `6:7` | Element Width for Source |
266 | EXTRA | `10:18` | Register Extra encoding |
267 | MODE | `19:23` | changes Vector behaviour |
269 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
270 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
271 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
272 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
273 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
275 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
277 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
281 Mode is an augmentation of SV behaviour. Different types of
282 instructions have different needs, similar to Power ISA
283 v3.1 64 bit prefix 8LS and MTRR formats apply to different
284 instruction types. Modes include Reduction, Iteration, arithmetic
285 saturation, and Fail-First. More specific details in each
286 section and in the [[svp64/appendix]]
288 * For condition register operations see [[sv/cr_ops]]
289 * For LD/ST Modes, see [[sv/ldst]].
290 * For Branch modes, see [[sv/branches]]
291 * For arithmetic and logical, see [[sv/normal]]
295 Default behaviour is set to 0b00 so that zeros follow the convention of
296 `scalar identity behaviour`. In this case it means that elwidth overrides
297 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
298 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
299 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
300 states that, again, the behaviour is not to be modified.
302 Only when elwidth is nonzero is the element width overridden to the
303 explicitly required value.
305 ## Elwidth for Integers:
307 | Value | Mnemonic | Description |
308 |-------|----------------|------------------------------------|
309 | 00 | DEFAULT | default behaviour for operation |
310 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
311 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
312 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
314 This encoding is chosen such that the byte width may be computed as
317 ## Elwidth for FP Registers:
319 | Value | Mnemonic | Description |
320 |-------|----------------|------------------------------------|
321 | 00 | DEFAULT | default behaviour for FP operation |
322 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
323 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
324 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
327 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
328 is reserved for a future implementation of SV
330 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
331 perform its operation at **half** the ELWIDTH then padded back out
332 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
333 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
334 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
335 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
336 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
337 (IEEE754 FP8 or BF8 are not defined).
341 Element-width overrides for CR Fields has no meaning. The bits
342 are therefore used for other purposes, or when Rc=1, the Elwidth
343 applies to the result being tested (a GPR or FPR), but not to the
348 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
349 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
350 lines up in combination with all other "default is all zeros" behaviour.
352 | Value | Mnemonic | Subvec | Description |
353 |-------|-----------|---------|------------------------|
354 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
355 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
356 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
357 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
359 The SUBVL encoding value may be thought of as an inclusive range of a
360 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
361 this may be considered to be elements 0b00 to 0b01 inclusive.
363 # MASK/MASK_SRC & MASKMODE Encoding
365 TODO: rename MASK_KIND to MASKMODE
367 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
368 types may not be mixed.
370 Special note: to disable predication this field must
371 be set to zero in combination with Integer Predication also being set
372 to 0b000. this has the effect of enabling "all 1s" in the predicate
373 mask, which is equivalent to "not having any predication at all"
374 and consequently, in combination with all other default zeros, fully
375 disables SV (`scalar identity behaviour`).
377 `MASKMODE` may be set to one of 2 values:
379 | Value | Description |
380 |-----------|------------------------------------------------------|
381 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
382 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
384 Integer Twin predication has a second set of 3 bits that uses the same
385 encoding thus allowing either the same register (r3, r10 or r31) to be used
386 for both src and dest, or different regs (one for src, one for dest).
388 Likewise CR based twin predication has a second set of 3 bits, allowing
389 a different test to be applied.
391 Note that it is assumed that Predicate Masks (whether INT or CR)
392 are read *before* the operations proceed. In practice (for CR Fields)
393 this creates an unnecessary block on parallelism. Therefore,
394 it is up to the programmer to ensure that the CR fields used as
395 Predicate Masks are not being written to by any parallel Vector Loop.
396 Doing so results in **UNDEFINED** behaviour, according to the definition
397 outlined in the Power ISA v3.0B Specification.
399 Hardware Implementations are therefore free and clear to delay reading
400 of individual CR fields until the actual predicated element operation
401 needs to take place, safe in the knowledge that no programmer will
402 have issued a Vector Instruction where previous elements could have
403 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
405 ## Integer Predication (MASKMODE=0)
407 When the predicate mode bit is zero the 3 bits are interpreted as below.
408 Twin predication has an identical 3 bit field similarly encoded.
410 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
412 | Value | Mnemonic | Element `i` enabled if: |
413 |-------|----------|------------------------------|
414 | 000 | ALWAYS | predicate effectively all 1s |
415 | 001 | 1 << R3 | `i == R3` |
416 | 010 | R3 | `R3 & (1 << i)` is non-zero |
417 | 011 | ~R3 | `R3 & (1 << i)` is zero |
418 | 100 | R10 | `R10 & (1 << i)` is non-zero |
419 | 101 | ~R10 | `R10 & (1 << i)` is zero |
420 | 110 | R30 | `R30 & (1 << i)` is non-zero |
421 | 111 | ~R30 | `R30 & (1 << i)` is zero |
423 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
425 ## CR-based Predication (MASKMODE=1)
427 When the predicate mode bit is one the 3 bits are interpreted as below.
428 Twin predication has an identical 3 bit field similarly encoded.
430 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
432 | Value | Mnemonic | Element `i` is enabled if |
433 |-------|----------|--------------------------|
434 | 000 | lt | `CR[offs+i].LT` is set |
435 | 001 | nl/ge | `CR[offs+i].LT` is clear |
436 | 010 | gt | `CR[offs+i].GT` is set |
437 | 011 | ng/le | `CR[offs+i].GT` is clear |
438 | 100 | eq | `CR[offs+i].EQ` is set |
439 | 101 | ne | `CR[offs+i].EQ` is clear |
440 | 110 | so/un | `CR[offs+i].FU` is set |
441 | 111 | ns/nu | `CR[offs+i].FU` is clear |
443 CR based predication. TODO: select alternate CR for twin predication? see
444 [[discussion]] Overlap of the two CR based predicates must be taken
445 into account, so the starting point for one of them must be suitably
446 high, or accept that for twin predication VL must not exceed the range
447 where overlap will occur, *or* that they use the same starting point
448 but select different *bits* of the same CRs
450 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
452 The CR Predicates chosen must start on a boundary that Vectorised
453 CR operations can access cleanly, in full.
454 With EXTRA2 restricting starting points
455 to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and CR Predicate
456 Masks have to be adapted to fit on these boundaries as well.
458 # Extra Remapped Encoding <a name="extra_remap"> </a>
460 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
462 These mappings are part of the SVP64 Specification in exactly the same
463 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
464 will need a corresponding SVP64 Mapping, which can be derived by-rote
465 from examining the Register "Profile" of the instruction.
467 There are two categories: Single and Twin Predication.
468 Due to space considerations further subdivision of Single Predication
469 is based on whether the number of src operands is 2 or 3. With only
470 9 bits available some compromises have to be made.
472 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
473 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
474 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
475 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
476 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
480 | Field Name | Field bits | Description |
481 |------------|------------|----------------------------------------|
482 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
483 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
484 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
485 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
486 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
488 These are for 3 operand in and either 1 or 2 out instructions.
489 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
490 such as `maddedu` have an implicit second destination, RS, the
491 selection of which is determined by bit 18.
495 | Field Name | Field bits | Description |
496 |------------|------------|-------------------------------------------|
497 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
498 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
499 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
501 These are for 2 operand 1 dest instructions, such as `add RT, RA,
502 RB`. However also included are unusual instructions with an implicit dest
503 that is identical to its src reg, such as `rlwinmi`.
505 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
506 an alternative destination. With SV however this becomes possible.
507 Therefore, the fact that the dest is implicitly also a src should not
508 mislead: due to the *prefix* they are different SV regs.
510 * `rlwimi RA, RS, ...`
511 * Rsrc1_EXTRA3 applies to RS as the first src
512 * Rsrc2_EXTRA3 applies to RA as the secomd src
513 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
515 With the addition of the EXTRA bits, the three registers
516 each may be *independently* made vector or scalar, and be independently
517 augmented to 7 bits in length.
521 | Field Name | Field bits | Description |
522 |------------|------------|----------------------------|
523 | Rdest_EXTRA3 | `10:12` | extends Rdest |
524 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
525 | MASK_SRC | `16:18` | Execution Mask for Source |
527 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
531 single-predicate, three registers (2 read, 1 write)
533 | Field Name | Field bits | Description |
534 |------------|------------|----------------------------|
535 | Rdest_EXTRA3 | `10:12` | extends Rdest |
536 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
537 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
539 ## RM-2P-2S1D/1S2D/3S
541 The primary purpose for this encoding is for Twin Predication on LOAD
542 and STORE operations. see [[sv/ldst]] for detailed anslysis.
546 | Field Name | Field bits | Description |
547 |------------|------------|----------------------------|
548 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
549 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
550 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
551 | MASK_SRC | `16:18` | Execution Mask for Source |
553 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
554 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
556 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
558 Note also that LD with update indexed, which takes 2 src and 2 dest
559 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
560 Twin Predication. therefore these are treated as RM-2P-2S1D and the
561 src spec for RA is also used for the same RA as a dest.
563 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
567 EXTRA is the means by which two things are achieved:
569 1. Registers are marked as either Vector *or Scalar*
570 2. Register field numbers (limited typically to 5 bit)
571 are extended in range, both for Scalar and Vector.
573 The register files are therefore extended:
575 * INT is extended from r0-31 to r0-127
576 * FP is extended from fp0-32 to fp0-fp127
577 * CR Fields are extended from CR0-7 to CR0-127
579 However due to pressure in `RM.EXTRA` not all these registers
580 are accessible by all instructions, particularly those with
581 a large number of operands (`madd`, `isel`).
583 In the following tables register numbers are constructed from the
584 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
585 or EXTRA3 field from the SV Prefix, determined by the specific
586 RM-xx-yyyy designation for a given instruction.
587 The prefixing is arranged so that
588 interoperability between prefixing and nonprefixing of scalar registers
589 is direct and convenient (when the EXTRA field is all zeros).
591 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
597 spec = EXTRA2 << 1 # same as EXTRA3, shifted
599 return (RA << 2) | spec[1:2]
601 return (spec[1:2] << 5) | RA
604 Future versions may extend to 256 by shifting Vector numbering up.
605 Scalar will not be altered.
607 Note that in some cases the range of starting points for Vectors
612 If EXTRA3 is zero, maps to
613 "scalar identity" (scalar Power ISA field naming).
615 Fields are as follows:
618 * Mode: register is tagged as scalar or vector
619 * Range/Inc: the range of registers accessible from this EXTRA
620 encoding, and the "increment" (accessibility). "/4" means
621 that this EXTRA encoding may only give access (starting point)
623 * MSB..LSB: the bit field showing how the register opcode field
624 combines with EXTRA to give (extend) the register number (GPR)
626 | Value | Mode | Range/Inc | 6..0 |
627 |-----------|-------|---------------|---------------------|
628 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
629 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
630 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
631 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
632 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
633 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
634 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
635 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
639 If EXTRA2 is zero will map to
640 "scalar identity behaviour" i.e Scalar Power ISA register naming:
642 | Value | Mode | Range/inc | 6..0 |
643 |-----------|-------|---------------|-----------|
644 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
645 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
646 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
647 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
649 **Note that unlike in EXTRA3, in EXTRA2**:
651 * the GPR Vectors may only start from
652 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
653 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
655 as there is insufficient bits to cover the full range.
659 CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
660 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
661 and Scalars may only go from `CR0, CR1, ... CR31`
663 Encoding shown MSB down to LSB
665 For a 5-bit operand (BA, BB, BT):
667 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
668 |-------|------|---------------|-----------| --------|---------|
669 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
670 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
671 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
672 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
673 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
674 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
675 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
676 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
678 For a 3-bit operand (e.g. BFA):
680 | Value | Mode | Range/Inc | 6..3 | 2..0 |
681 |-------|------|---------------|-----------| --------|
682 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
683 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
684 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
685 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
686 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
687 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
688 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
689 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
693 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
694 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
697 Encoding shown MSB down to LSB
699 For a 5-bit operand (BA, BB, BC):
701 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
702 |-------|--------|----------------|---------|---------|---------|
703 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
704 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
705 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
706 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
708 For a 3-bit operand (e.g. BFA):
710 | Value | Mode | Range/Inc | 6..3 | 2..0 |
711 |-------|------|---------------|-----------| --------|
712 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
713 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
714 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
715 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
719 Now at its own page: [[svp64/appendix]]