1 # RFC ls009 SVP64 Zero-Overhead Loop Prefix Subsystem
3 Credits and acknowledgements:
11 * NLnet Foundation, for funding
12 * OpenPOWER Foundation
15 * IBM for the Power ISA itself
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
23 Simple-V is a type of Vectorisation best described as a "Prefix Loop Subsystem"
24 similar to the Z80 `LDIR` instruction and to the x86 `REP` Prefix instruction.
25 More advanced features are similar to the Z80 `CPIR` instruction. If viewed
26 as an actual Vector ISA it introduces over 1.5 million 64-bit Vector instructions.
27 SVP64, the instruction format, is therefore best viewed as an orthogonal
28 RISC-style "Prefixing" subsystem instead.
30 Except where explicitly stated all bit numbers remain as in the rest of the Power ISA:
31 in MSB0 form (the bits are numbered from 0 at the MSB on the left
32 and counting up as you move rightwards to the LSB end). All bit ranges are inclusive
33 (so `4:6` means bits 4, 5, and 6, in MSB0 order). **All register numbering and
34 element numbering however is LSB0 ordering** which is a different convention from that used
35 elsewhere in the Power ISA.
37 64-bit instructions are split into two 32-bit words, the prefix and the
38 suffix. The prefix always comes before the suffix in PC order.
40 | 0:5 | 6:31 | 32:63 |
41 |--------|--------------|--------------|
42 | EXT09 | v3.1 Prefix | v3.0/1 Suffix |
44 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
46 Subset implementations in hardware are permitted, as long as certain
47 rules are followed, allowing for full soft-emulation including future
48 revisions. Compliancy Subsets exist to ensure minimum levels of binary
49 interoperability expectations within certain environments.
51 ## Register files, elements, and Element-width Overrides
53 In the Upper Compliancy Levels the size of the GPR and FPR Register files are expanded
54 from 32 to 128 entries, and the number of CR Fields expanded from CR0-CR7 to CR0-CR127.
56 Memory access remains exactly the same: the effects of `MSR.LE` remain exactly the same,
57 affecting as they already do and remain **only** on the Load and Store memory-register
58 operation byte-order, and having nothing to do with the
59 ordering of the contents of register files or register-register operations.
61 Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered and for
62 numbering to be sequentially incremental the element offset numbering is naturally
63 **LSB0-sequentially-incrementing from zero not MSB0-incrementing.** Expressed exclusively in
64 MSB0-numbering, SVP64 is unnecessarily complex to understand: the required
65 subtractions from 63, 31, 15 and 7 unfortunately become a hostile minefield.
66 Therefore for the purposes of this section the more natural
67 **LSB0 numbering is assumed** and it is up to the reader to translate to MSB0 numbering.
69 The Canonical specification for how element-sequential numbering and element-width
70 overrides is defined is expressed in the following c structure, assuming a Little-Endian
71 system, and naturally using LSB0 numbering everywhere because the ANSI c specification
77 uint8_t b[]; // elwidth 8
78 uint16_t s[]; // elwidth 16
79 uint32_t i[]; // elwidth 32
80 uint64_t l[]; // elwidth 64
81 uint8_t actual_bytes[8];
84 elreg_t int_regfile[128];
86 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
88 case 64: el->l = int_regfile[gpr].l[element];
89 case 32: el->i = int_regfile[gpr].i[element];
90 case 16: el->s = int_regfile[gpr].s[element];
91 case 8 : el->b = int_regfile[gpr].b[element];
94 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
96 case 64: int_regfile[gpr].l[element] = el->l;
97 case 32: int_regfile[gpr].i[element] = el->i;
98 case 16: int_regfile[gpr].s[element] = el->s;
99 case 8 : int_regfile[gpr].b[element] = el->b;
104 Example add operation implementation when elwidths are 64-bit:
107 # add RT, RA,RB using the "uint64_t" union member, "l"
109 int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
112 However if elwidth overrides are set to 16 for both source and destination:
115 # add RT, RA, RB using the "uint64_t" union member "s"
117 int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
120 Hardware Architectural note: to avoid a Read-Modify-Write at the register file it is
121 strongly recommended to implement byte-level write-enable lines exactly as has been
122 implemented in DRAM ICs for many decades. Additionally the predicate mask bit is advised
123 to be associated with the element operation and ultimately passed to the register file.
124 When element-width is set to 64-bit the relevant predicate mask bit may be repeated
125 eight times and pull all eight write-port byte-level lines HIGH. Clearly when element-width
126 is set to 8-bit the relevant predicate mask bit corresponds directly with one single
127 byte-level write-enable line. It is up to the Hardware Architect to then amortise (merge)
128 elements together into both PredicatedSIMD Pipelines as well as simultaneous non-overlapping
129 Register File writes, to achieve High Performance designs.
131 ## SVP64 encoding features
133 A number of features need to be compacted into a very small space of only 24 bits:
135 * Independent per-register Scalar/Vector tagging and range extension on every register
136 * Element width overrides on both source and destination
137 * Predication on both source and destination
138 * Two different sources of predication: INT and CR Fields
139 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
140 predicate-result mode.
142 Different classes of operations require
144 # Definition of Reserved in this spec.
146 For the new fields added in SVP64, instructions that have any of their
147 fields set to a reserved value must cause an illegal instruction trap,
148 to allow emulation of future instruction sets, or for subsets of SVP64
149 to be implemented in hardware and the rest emulated.
150 This includes SVP64 SPRs: reading or writing values which are not
151 supported in hardware must also raise illegal instruction traps
152 in order to allow emulation.
153 Unless otherwise stated, reserved values are always all zeros.
155 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard Power ISA definition
156 is intended the red keyword `RESERVED` is used.
158 # Definition of "UnVectoriseable"
160 Any operation that inherently makes no sense if repeated is termed "UnVectoriseable"
161 or "UnVectorised". Examples include `sc` or `sync` which have no registers. `mtmsr` is
162 also classed as UnVectoriseable because there is only one `MSR`.
164 # Scalar Identity Behaviour
166 SVP64 is designed so that when the prefix is all zeros, and
168 influence occurs (no augmentation) such that all standard Power ISA
169 v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
171 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
172 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
174 # Register Naming and size
176 SV Registers are simply the INT, FP and CR register files extended
177 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
179 Where the integer regfile in standard scalar
180 Power ISA v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
181 Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields
183 extended to 128 entries, CR0 thru CR127.
185 The names of the registers therefore reflects a simple linear extension
186 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
187 would be reflected by a linear increase in the size of the underlying
188 SRAM used for the regfiles.
190 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
191 so that the register fields are identical to as if SV was not in effect
192 i.e. under these circumstances (EXTRA=0) the register field names RA,
193 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
194 `scalar identity behaviour` described above.
198 With the way that EXTRA fields are defined and applied to register fields,
199 future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Further discussion is out of scope for this version of SVP64.
201 # Remapped Encoding (`RM[0:23]`)
203 To allow relatively easy remapping of which portions of the Prefix Opcode
204 Map are used for SVP64 without needing to rewrite a large portion of the
205 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
206 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
209 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
210 is defined in the Prefix Fields section.
212 ## Prefix Opcode Map (64-bit instruction encoding)
214 In the original table in the v3.1B Power ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
216 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
217 empty spaces are yet-to-be-allocated Illegal Instructions.
219 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
220 |------|--------|--------|--------|--------|--------|--------|--------|--------|
221 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
222 |001---| | | | | | | | |
223 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
224 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
225 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
226 |101---| | | | | | | | |
227 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
228 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
230 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
234 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
235 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
236 This is achieved by setting bits 7 and 9 to 1:
238 | Name | Bits | Value | Description |
239 |------------|---------|-------|--------------------------------|
240 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
241 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
242 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
243 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
244 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
245 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
247 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
250 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
251 |--------|-------|---|-------|---|----------|
252 | EXT01 | RM | 1 | RM | 1 | RM |
253 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
255 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
256 instruction. That instruction becomes "prefixed" with the SVP context: the
257 Remapped Encoding field (RM).
259 It is important to note that unlike v3.1 64-bit prefixed instructions
260 there is insufficient space in `RM` to provide identification of
261 any SVP64 Fields without first partially decoding the
262 32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
263 `RM` format is individually associated with every instruction.
265 Extreme caution and care must therefore be taken
266 when extending SVP64 in future, to not create unnecessary relationships
267 between prefix and suffix that could complicate decoding, adding latency.
271 The following fields are common to all Remapped Encodings:
273 | Field Name | Field bits | Description |
274 |------------|------------|----------------------------------------|
275 | MASKMODE | `0` | Execution (predication) Mask Kind |
276 | MASK | `1:3` | Execution Mask |
277 | SUBVL | `8:9` | Sub-vector length |
279 The following fields are optional or encoded differently depending
280 on context after decoding of the Scalar suffix:
282 | Field Name | Field bits | Description |
283 |------------|------------|----------------------------------------|
284 | ELWIDTH | `4:5` | Element Width |
285 | ELWIDTH_SRC | `6:7` | Element Width for Source |
286 | EXTRA | `10:18` | Register Extra encoding |
287 | MODE | `19:23` | changes Vector behaviour |
289 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
290 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
291 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
292 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
293 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
295 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
297 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
301 Mode is an augmentation of SV behaviour. Different types of
302 instructions have different needs, similar to Power ISA
303 v3.1 64 bit prefix 8LS and MTRR formats apply to different
304 instruction types. Modes include Reduction, Iteration, arithmetic
305 saturation, and Fail-First. More specific details in each
306 section and in the [[svp64/appendix]]
308 * For condition register operations see [[sv/cr_ops]]
309 * For LD/ST Modes, see [[sv/ldst]].
310 * For Branch modes, see [[sv/branches]]
311 * For arithmetic and logical, see [[sv/normal]]
315 Default behaviour is set to 0b00 so that zeros follow the convention of
316 `scalar identity behaviour`. In this case it means that elwidth overrides
317 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
318 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
319 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
320 states that, again, the behaviour is not to be modified.
322 Only when elwidth is nonzero is the element width overridden to the
323 explicitly required value.
325 ## Elwidth for Integers:
327 | Value | Mnemonic | Description |
328 |-------|----------------|------------------------------------|
329 | 00 | DEFAULT | default behaviour for operation |
330 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
331 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
332 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
334 This encoding is chosen such that the byte width may be computed as
337 ## Elwidth for FP Registers:
339 | Value | Mnemonic | Description |
340 |-------|----------------|------------------------------------|
341 | 00 | DEFAULT | default behaviour for FP operation |
342 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
343 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
344 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
347 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
348 is reserved for a future implementation of SV
350 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
351 perform its operation at **half** the ELWIDTH then padded back out
352 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
353 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
354 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
355 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
356 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
357 (IEEE754 FP8 or BF8 are not defined).
361 Element-width overrides for CR Fields has no meaning. The bits
362 are therefore used for other purposes, or when Rc=1, the Elwidth
363 applies to the result being tested (a GPR or FPR), but not to the
368 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
369 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
370 lines up in combination with all other "default is all zeros" behaviour.
372 | Value | Mnemonic | Subvec | Description |
373 |-------|-----------|---------|------------------------|
374 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
375 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
376 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
377 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
379 The SUBVL encoding value may be thought of as an inclusive range of a
380 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
381 this may be considered to be elements 0b00 to 0b01 inclusive.
383 # MASK/MASK_SRC & MASKMODE Encoding
385 TODO: rename MASK_KIND to MASKMODE
387 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
388 types may not be mixed.
390 Special note: to disable predication this field must
391 be set to zero in combination with Integer Predication also being set
392 to 0b000. this has the effect of enabling "all 1s" in the predicate
393 mask, which is equivalent to "not having any predication at all"
394 and consequently, in combination with all other default zeros, fully
395 disables SV (`scalar identity behaviour`).
397 `MASKMODE` may be set to one of 2 values:
399 | Value | Description |
400 |-----------|------------------------------------------------------|
401 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
402 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
404 Integer Twin predication has a second set of 3 bits that uses the same
405 encoding thus allowing either the same register (r3, r10 or r31) to be used
406 for both src and dest, or different regs (one for src, one for dest).
408 Likewise CR based twin predication has a second set of 3 bits, allowing
409 a different test to be applied.
411 Note that it is assumed that Predicate Masks (whether INT or CR)
412 are read *before* the operations proceed. In practice (for CR Fields)
413 this creates an unnecessary block on parallelism. Therefore,
414 it is up to the programmer to ensure that the CR fields used as
415 Predicate Masks are not being written to by any parallel Vector Loop.
416 Doing so results in **UNDEFINED** behaviour, according to the definition
417 outlined in the Power ISA v3.0B Specification.
419 Hardware Implementations are therefore free and clear to delay reading
420 of individual CR fields until the actual predicated element operation
421 needs to take place, safe in the knowledge that no programmer will
422 have issued a Vector Instruction where previous elements could have
423 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
425 ## Integer Predication (MASKMODE=0)
427 When the predicate mode bit is zero the 3 bits are interpreted as below.
428 Twin predication has an identical 3 bit field similarly encoded.
430 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
432 | Value | Mnemonic | Element `i` enabled if: |
433 |-------|----------|------------------------------|
434 | 000 | ALWAYS | predicate effectively all 1s |
435 | 001 | 1 << R3 | `i == R3` |
436 | 010 | R3 | `R3 & (1 << i)` is non-zero |
437 | 011 | ~R3 | `R3 & (1 << i)` is zero |
438 | 100 | R10 | `R10 & (1 << i)` is non-zero |
439 | 101 | ~R10 | `R10 & (1 << i)` is zero |
440 | 110 | R30 | `R30 & (1 << i)` is non-zero |
441 | 111 | ~R30 | `R30 & (1 << i)` is zero |
443 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
445 ## CR-based Predication (MASKMODE=1)
447 When the predicate mode bit is one the 3 bits are interpreted as below.
448 Twin predication has an identical 3 bit field similarly encoded.
450 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
452 | Value | Mnemonic | Element `i` is enabled if |
453 |-------|----------|--------------------------|
454 | 000 | lt | `CR[offs+i].LT` is set |
455 | 001 | nl/ge | `CR[offs+i].LT` is clear |
456 | 010 | gt | `CR[offs+i].GT` is set |
457 | 011 | ng/le | `CR[offs+i].GT` is clear |
458 | 100 | eq | `CR[offs+i].EQ` is set |
459 | 101 | ne | `CR[offs+i].EQ` is clear |
460 | 110 | so/un | `CR[offs+i].FU` is set |
461 | 111 | ns/nu | `CR[offs+i].FU` is clear |
463 CR based predication. TODO: select alternate CR for twin predication? see
464 [[discussion]] Overlap of the two CR based predicates must be taken
465 into account, so the starting point for one of them must be suitably
466 high, or accept that for twin predication VL must not exceed the range
467 where overlap will occur, *or* that they use the same starting point
468 but select different *bits* of the same CRs
470 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
472 The CR Predicates chosen must start on a boundary that Vectorised
473 CR operations can access cleanly, in full.
474 With EXTRA2 restricting starting points
475 to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and CR Predicate
476 Masks have to be adapted to fit on these boundaries as well.
478 # Extra Remapped Encoding <a name="extra_remap"> </a>
480 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
482 These mappings are part of the SVP64 Specification in exactly the same
483 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
484 will need a corresponding SVP64 Mapping, which can be derived by-rote
485 from examining the Register "Profile" of the instruction.
487 There are two categories: Single and Twin Predication.
488 Due to space considerations further subdivision of Single Predication
489 is based on whether the number of src operands is 2 or 3. With only
490 9 bits available some compromises have to be made.
492 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
493 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
494 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
495 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
496 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
500 | Field Name | Field bits | Description |
501 |------------|------------|----------------------------------------|
502 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
503 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
504 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
505 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
506 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
508 These are for 3 operand in and either 1 or 2 out instructions.
509 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
510 such as `maddedu` have an implicit second destination, RS, the
511 selection of which is determined by bit 18.
515 | Field Name | Field bits | Description |
516 |------------|------------|-------------------------------------------|
517 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
518 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
519 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
521 These are for 2 operand 1 dest instructions, such as `add RT, RA,
522 RB`. However also included are unusual instructions with an implicit dest
523 that is identical to its src reg, such as `rlwinmi`.
525 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
526 an alternative destination. With SV however this becomes possible.
527 Therefore, the fact that the dest is implicitly also a src should not
528 mislead: due to the *prefix* they are different SV regs.
530 * `rlwimi RA, RS, ...`
531 * Rsrc1_EXTRA3 applies to RS as the first src
532 * Rsrc2_EXTRA3 applies to RA as the secomd src
533 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
535 With the addition of the EXTRA bits, the three registers
536 each may be *independently* made vector or scalar, and be independently
537 augmented to 7 bits in length.
541 | Field Name | Field bits | Description |
542 |------------|------------|----------------------------|
543 | Rdest_EXTRA3 | `10:12` | extends Rdest |
544 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
545 | MASK_SRC | `16:18` | Execution Mask for Source |
547 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
551 single-predicate, three registers (2 read, 1 write)
553 | Field Name | Field bits | Description |
554 |------------|------------|----------------------------|
555 | Rdest_EXTRA3 | `10:12` | extends Rdest |
556 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
557 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
559 ## RM-2P-2S1D/1S2D/3S
561 The primary purpose for this encoding is for Twin Predication on LOAD
562 and STORE operations. see [[sv/ldst]] for detailed anslysis.
566 | Field Name | Field bits | Description |
567 |------------|------------|----------------------------|
568 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
569 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
570 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
571 | MASK_SRC | `16:18` | Execution Mask for Source |
573 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
574 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
576 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
578 Note also that LD with update indexed, which takes 2 src and 2 dest
579 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
580 Twin Predication. therefore these are treated as RM-2P-2S1D and the
581 src spec for RA is also used for the same RA as a dest.
583 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
587 EXTRA is the means by which two things are achieved:
589 1. Registers are marked as either Vector *or Scalar*
590 2. Register field numbers (limited typically to 5 bit)
591 are extended in range, both for Scalar and Vector.
593 The register files are therefore extended:
595 * INT is extended from r0-31 to r0-127
596 * FP is extended from fp0-32 to fp0-fp127
597 * CR Fields are extended from CR0-7 to CR0-127
599 However due to pressure in `RM.EXTRA` not all these registers
600 are accessible by all instructions, particularly those with
601 a large number of operands (`madd`, `isel`).
603 In the following tables register numbers are constructed from the
604 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
605 or EXTRA3 field from the SV Prefix, determined by the specific
606 RM-xx-yyyy designation for a given instruction.
607 The prefixing is arranged so that
608 interoperability between prefixing and nonprefixing of scalar registers
609 is direct and convenient (when the EXTRA field is all zeros).
611 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
617 spec = EXTRA2 << 1 # same as EXTRA3, shifted
619 return (RA << 2) | spec[1:2]
621 return (spec[1:2] << 5) | RA
624 Future versions may extend to 256 by shifting Vector numbering up.
625 Scalar will not be altered.
627 Note that in some cases the range of starting points for Vectors
632 If EXTRA3 is zero, maps to
633 "scalar identity" (scalar Power ISA field naming).
635 Fields are as follows:
638 * Mode: register is tagged as scalar or vector
639 * Range/Inc: the range of registers accessible from this EXTRA
640 encoding, and the "increment" (accessibility). "/4" means
641 that this EXTRA encoding may only give access (starting point)
643 * MSB..LSB: the bit field showing how the register opcode field
644 combines with EXTRA to give (extend) the register number (GPR)
646 | Value | Mode | Range/Inc | 6..0 |
647 |-----------|-------|---------------|---------------------|
648 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
649 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
650 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
651 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
652 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
653 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
654 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
655 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
659 If EXTRA2 is zero will map to
660 "scalar identity behaviour" i.e Scalar Power ISA register naming:
662 | Value | Mode | Range/inc | 6..0 |
663 |-----------|-------|---------------|-----------|
664 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
665 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
666 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
667 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
669 **Note that unlike in EXTRA3, in EXTRA2**:
671 * the GPR Vectors may only start from
672 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
673 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
675 as there is insufficient bits to cover the full range.
679 CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
680 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
681 and Scalars may only go from `CR0, CR1, ... CR31`
683 Encoding shown MSB down to LSB
685 For a 5-bit operand (BA, BB, BT):
687 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
688 |-------|------|---------------|-----------| --------|---------|
689 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
690 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
691 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
692 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
693 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
694 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
695 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
696 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
698 For a 3-bit operand (e.g. BFA):
700 | Value | Mode | Range/Inc | 6..3 | 2..0 |
701 |-------|------|---------------|-----------| --------|
702 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
703 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
704 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
705 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
706 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
707 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
708 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
709 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
713 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
714 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
717 Encoding shown MSB down to LSB
719 For a 5-bit operand (BA, BB, BC):
721 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
722 |-------|--------|----------------|---------|---------|---------|
723 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
724 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
725 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
726 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
728 For a 3-bit operand (e.g. BFA):
730 | Value | Mode | Range/Inc | 6..3 | 2..0 |
731 |-------|------|---------------|-----------| --------|
732 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
733 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
734 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
735 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
739 Now at its own page: [[svp64/appendix]]