1 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
3 Credits and acknowledgements:
11 * NLnet Foundation, for funding
12 * OpenPOWER Foundation
15 * IBM for the Power ISA itself
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
23 Simple-V is a type of Vectorisation best described as a "Prefix Loop
24 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the 8086 `REP`
25 Prefix instruction. More advanced features are similar to the Z80
26 `CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces
27 over 1.5 million 64-bit Vector instructions. SVP64, the instruction
28 format, is therefore best viewed as an orthogonal RISC-paradigm "Prefixing"
31 Except where explicitly stated all bit numbers remain as in the rest of
32 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
33 the left and counting up as you move rightwards to the LSB end). All bit
34 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
35 **All register numbering and element numbering however is LSB0 ordering**
36 which is a different convention from that used elsewhere in the Power ISA.
38 The SVP64 prefix always comes before the suffix in PC order and must be
39 considered an independent "Defined word" that augments the behaviour of
40 the following instruction, but does **not** change the actual Decoding
41 of that following instruction. **All prefixed instructions retain their
42 non-prefixed encoding and definition**.
44 Two apparent exceptions to the above hard rule exist: SV Branch-Conditional
45 operations and LD/ST-update "Post-Increment" Mode. Post-Increment
46 was considered sufficiently high priority (significantly reducing hot-loop
47 instruction count) that one bit in the Prefix is reserved for it.
48 Vectorised Branch-Conditional operations "embed" the original Scalar
49 Branch-Conditional behaviour into a much more advanced variant that
50 is highly suited to High-Performance Computation (HPC), Supercomputing,
51 and parallel GPU Workloads.
53 *Architectural Resource Allocation note: it is prohibited to accept RFCs
54 which fundamentally violate this hard requirement. Under no circumstances
55 must the Suffix space have an alternate instruction encoding allocated
56 within SVP64 that is entirely different from the non-prefixed Defined
57 Word. Hardware Implementors critically rely on this inviolate guarantee
58 to implement High-Performance Multi-Issue micro-architectures that can
59 sustain 100% throughput*
61 Subset implementations in hardware are permitted, as long as certain
62 rules are followed, allowing for full soft-emulation including future
63 revisions. Compliancy Subsets exist to ensure minimum levels of binary
64 interoperability expectations within certain environments.
66 ## SVP64 encoding features
68 A number of features need to be compacted into a very small space of
71 * Independent per-register Scalar/Vector tagging and range extension on
73 * Element width overrides on both source and destination
74 * Predication on both source and destination
75 * Two different sources of predication: INT and CR Fields
76 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
77 fail-first and predicate-result mode.
79 Different classes of operations require different formats. The earlier
80 sections cover the common formats and the four separate modes follow:
81 CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
82 and Branch-Conditional.
84 ## Definition of Reserved in this spec.
86 For the new fields added in SVP64, instructions that have any of their
87 fields set to a reserved value must cause an illegal instruction trap,
88 to allow emulation of future instruction sets, or for subsets of SVP64 to
89 be implemented in hardware and the rest emulated. This includes SVP64
90 SPRs: reading or writing values which are not supported in hardware
91 must also raise illegal instruction traps in order to allow emulation.
92 Unless otherwise stated, reserved values are always all zeros.
94 This is unlike OpenPower ISA v3.1, which in many instances does not
95 require a trap if reserved fields are nonzero. Where the standard Power
96 ISA definition is intended the red keyword `RESERVED` is used.
98 ## Definition of "UnVectoriseable"
100 Any operation that inherently makes no sense if repeated is termed
101 "UnVectoriseable" or "UnVectorised". Examples include `sc` or `sync`
102 which have no registers. `mtmsr` is also classed as UnVectoriseable
103 because there is only one `MSR`.
105 ## Register files, elements, and Element-width Overrides
107 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR Register
108 files are expanded from 32 to 128 entries, and the number of CR Fields
109 expanded from CR0-CR7 to CR0-CR127. (Note: A future version of SVP64 is anticipated
110 to extend the VSR register file).
112 Memory access remains exactly the same: the effects of `MSR.LE` remain
113 exactly the same, affecting as they already do and remain **only**
114 on the Load and Store memory-register operation byte-order, and having
115 nothing to do with the ordering of the contents of register files or
116 register-register operations.
118 To be absolutely clear:
121 No conceptual arithmetic ordering or other changes over the Scalar
122 Power ISA definitions to registers or register files or to arithmetic
123 or Logical Operations beyond element-width subdivision and sequential
124 element numbering are expressed or implied
128 numbering is naturally **LSB0-sequentially-incrementing from zero, not
129 MSB0-incrementing** including when element-width overrides are used,
130 at which point the elements progress through each register
131 sequentially from the LSB end
132 (confusingly numbered the highest in MSB0 ordering) and progress
133 incrementally to the MSB end (confusingly numbered the lowest in
136 When exclusively using MSB0-numbering, SVP64
137 becomes unnecessarily complex to both express and subsequently understand:
138 the required conditional subtractions from 63,
139 31, 15 and 7 unfortunately become a hostile minefield, obscuring both
140 intent and meaning. Therefore for the
141 purposes of this section the more natural **LSB0 numbering is assumed**
142 and it is left to the reader to translate to MSB0 numbering.
144 The Canonical specification for how element-sequential numbering and
145 element-width overrides is defined is expressed in the following c
146 structure, assuming a Little-Endian system, and naturally using LSB0
147 numbering everywhere because the ANSI c specification is inherently LSB0:
152 uint8_t b[]; // elwidth 8
153 uint16_t s[]; // elwidth 16
154 uint32_t i[]; // elwidth 32
155 uint64_t l[]; // elwidth 64
156 uint8_t actual_bytes[8];
159 elreg_t int_regfile[128];
161 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
163 case 64: el->l = int_regfile[gpr].l[element];
164 case 32: el->i = int_regfile[gpr].i[element];
165 case 16: el->s = int_regfile[gpr].s[element];
166 case 8 : el->b = int_regfile[gpr].b[element];
169 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
171 case 64: int_regfile[gpr].l[element] = el->l;
172 case 32: int_regfile[gpr].i[element] = el->i;
173 case 16: int_regfile[gpr].s[element] = el->s;
174 case 8 : int_regfile[gpr].b[element] = el->b;
179 Example Vector-looped add operation implementation when elwidths are 64-bit:
182 # add RT, RA,RB using the "uint64_t" union member, "l"
184 int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
187 However if elwidth overrides are set to 16 for both source and destination:
190 # add RT, RA, RB using the "uint64_t" union member "s"
192 int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
195 Hardware Architectural note: to avoid a Read-Modify-Write at the register
196 file it is strongly recommended to implement byte-level write-enable lines
197 exactly as has been implemented in DRAM ICs for many decades. Additionally
198 the predicate mask bit is advised to be associated with the element
199 operation and alongside the result ultimately passed to the register file.
200 When element-width is set to 64-bit the relevant predicate mask bit
201 may be repeated eight times and pull all eight write-port byte-level
202 lines HIGH. Clearly when element-width is set to 8-bit the relevant
203 predicate mask bit corresponds directly with one single byte-level
204 write-enable line. It is up to the Hardware Architect to then amortise
205 (merge) elements together into both PredicatedSIMD Pipelines as well
206 as simultaneous non-overlapping Register File writes, to achieve High
209 ## Scalar Identity Behaviour
211 SVP64 is designed so that when the prefix is all zeros, and
213 influence occurs (no augmentation) such that all standard Power ISA
214 v3.0/v3 1 instructions covered by the prefix are "unaltered". This
215 is termed `scalar identity behaviour` (based on the mathematical
216 definition for "identity", as in, "identity matrix" or better "identity
219 Note that this is completely different from when VL=0. VL=0 turns all
220 operations under its influence into `nops` (regardless of the prefix)
221 whereas when VL=1 and the SV prefix is all zeros, the operation simply
222 acts as if SV had not been applied at all to the instruction (an
223 "identity transformation").
225 The fact that `VL` is dynamic and can be set to any value at runtime based
226 on program conditions and behaviour means very specifically that
227 `scalar identity behaviour` is **not** a redundant encoding. If the
228 only means by which VL could be set was by way of static-compiled
229 immediates then this assertion would be false. VL should not
230 be confused with MAXVL when understanding this key aspect of SimpleV.
232 ## Register Naming and size
234 As indicated above SV Registers are simply the GPR, FPR and CR
235 register files extended linearly to larger sizes; SV Vectorisation
236 iterates sequentially through these registers (LSB0 sequential ordering
239 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
240 r0 to r31, SV extends this as r0 to r127. Likewise FP registers are
241 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
244 The names of the registers therefore reflects a simple linear extension
245 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
246 would be reflected by a linear increase in the size of the underlying
247 SRAM used for the regfiles.
249 Note: when an EXTRA field (defined below) is zero, SV is deliberately
250 designed so that the register fields are identical to as if SV was not in
251 effect i.e. under these circumstances (EXTRA=0) the register field names
252 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
253 This is part of `scalar identity behaviour` described above.
257 With the way that EXTRA fields are defined and applied to register fields,
258 future versions of SV may involve 256 or greater registers. Backwards
259 binary compatibility may be achieved with a PCR bit (Program Compatibility
260 Register). Further discussion is out of scope for this version of SVP64.
262 Additionally, a future variant of SVP64 will be applied to the Scalar
263 (Quad-precision and 128-bit) VSX instructions. Element-width overrides
264 are an opportunity to expand the Power ISA to 256-bit, 512-bit and
271 # New 64-bit Instruction Encoding spaces
273 The following seven new areas are defined within Primary Opcode 9 (EXT009) as a
274 new 64-bit encoding space, alongside EXT1xx.
276 | 0-5 | 6 | 7 | 8-31 | 32| Description |
277 |-----|---|---|-------|---|------------------------------------|
278 | PO | 0 | x | xxxx | 0 | EXT200-232 or `RESERVED2` (56-bit) |
279 | PO | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
280 | PO | 0 | 0 | 0000 | 1 | Scalar EXT232-263 |
281 | PO | 0 | 1 | nnnn | 1 | SVP64:EXT232-263 |
282 | PO | 1 | 0 | 0000 | x | EXT300-363 or `RESERVED1` (32-bit) |
283 | PO | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
284 | PO | 1 | 1 | nnnn | n | SVP64:EXT000-063 |
286 Note that for the future SVP64Single Encoding (currently RESERVED) it
287 is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
289 can be zero (termed `scalar identity behaviour`). This
290 prohibition allows SVP64Single to share its
291 Encoding space with Scalar Ext232-263 and Scalar EXT300-363.
293 *Architectural Resource Allocation Note: **under no circumstances** must
294 different Defined Words be allocated within any `EXT{z}` prefixed
295 or unprefixed space for a given value of `z`. Even if UnVectoriseable
296 an instruction Defined Word space must have the exact same Instruction
297 and exact same Instruction Encoding in all spaces (including
298 being RESERVED if UnVectoriseable) or not be allocated at all.
299 This is required as an inviolate hard rule governing Primary Opcode 9
300 that may not be revoked under any circumstances. A useful way to think
301 of this is that the Prefix Encoding is, like the 8086 REP instruction,
302 an independent 32-bit Defined Word.*
304 # Remapped Encoding (`RM[0:23]`)
306 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits 32-37 are
307 the Primary Opcode of the Suffix "Defined Word". 38-63 are the remainder of the
308 Defined Word. Note that the new EXT232-263 SVP64 area it is obviously mandatory
309 that bit 32 is required to be set to 1.
311 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
312 |-----|---|---|----------|--------|----------|-----------------------|
313 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
314 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
316 It is important to note that unlike v3.1 64-bit prefixed instructions
317 there is insufficient space in `RM` to provide identification of any SVP64
318 Fields without first partially decoding the 32-bit suffix. Similar to
319 the "Forms" (X-Form, D-Form) the `RM` format is individually associated
320 with every instruction. However this still does not adversely affect Multi-Issue
321 Decoding because the identification of the 64-bit space has been kept brutally
324 Extreme caution and care must be taken when extending SVP64
325 in future, to not create unnecessary relationships between prefix and
326 suffix that could complicate decoding, adding latency.
330 The following fields are common to all Remapped Encodings:
332 | Field Name | Field bits | Description |
333 |------------|------------|----------------------------------------|
334 | MASKMODE | `0` | Execution (predication) Mask Kind |
335 | MASK | `1:3` | Execution Mask |
336 | SUBVL | `8:9` | Sub-vector length |
338 The following fields are optional or encoded differently depending
339 on context after decoding of the Scalar suffix:
341 | Field Name | Field bits | Description |
342 |------------|------------|----------------------------------------|
343 | ELWIDTH | `4:5` | Element Width |
344 | ELWIDTH_SRC | `6:7` | Element Width for Source |
345 | EXTRA | `10:18` | Register Extra encoding |
346 | MODE | `19:23` | changes Vector behaviour |
348 * MODE changes the behaviour of the SV operation (result saturation,
350 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
351 and Audio/Video DSP work
352 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
354 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
355 sources: scalar INT and Vector CR).
356 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
357 for the instruction, which is determined only by decoding the Scalar 32
360 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
361 such as `RM-1P-3S1D` which indicates for this example that the operation
362 is to be single-predicated and that there are 3 source operand EXTRA
363 tags and one destination operand tag.
365 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
366 or increased latency in some implementations due to lane-crossing.
370 Mode is an augmentation of SV behaviour. Different types of instructions
371 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
372 formats apply to different instruction types. Modes include Reduction,
373 Iteration, arithmetic saturation, and Fail-First. More specific details
374 in each section and in the SVP64 appendix
376 * For condition register operations see [[sv/cr_ops]]
377 * For LD/ST Modes, see [[sv/ldst]].
378 * For Branch modes, see [[sv/branches]]
379 * For arithmetic and logical, see [[sv/normal]]
383 Default behaviour is set to 0b00 so that zeros follow the convention
384 of `scalar identity behaviour`. In this case it means that elwidth
385 overrides are not applicable. Thus if a 32 bit instruction operates
386 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
387 Likewise when a processor is switched from 64 bit to 32 bit mode,
388 `elwidth=0b00` states that, again, the behaviour is not to be modified.
390 Only when elwidth is nonzero is the element width overridden to the
391 explicitly required value.
393 ### Elwidth for Integers:
395 | Value | Mnemonic | Description |
396 |-------|----------------|------------------------------------|
397 | 00 | DEFAULT | default behaviour for operation |
398 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
399 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
400 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
402 This encoding is chosen such that the byte width may be computed as
405 ### Elwidth for FP Registers:
407 | Value | Mnemonic | Description |
408 |-------|----------------|------------------------------------|
409 | 00 | DEFAULT | default behaviour for FP operation |
410 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
411 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
412 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
415 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
416 is reserved for a future implementation of SV
418 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
419 perform its operation at **half** the ELWIDTH then padded back out
420 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
421 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
422 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
423 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
424 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
425 (IEEE754 FP8 or BF8 are not defined).
427 ### Elwidth for CRs (no meaning)
429 Element-width overrides for CR Fields has no meaning. The bits
430 are therefore used for other purposes, or when Rc=1, the Elwidth
431 applies to the result being tested (a GPR or FPR), but not to the
436 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
437 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
438 lines up in combination with all other "default is all zeros" behaviour.
440 | Value | Mnemonic | Subvec | Description |
441 |-------|-----------|---------|------------------------|
442 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
443 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
444 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
445 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
447 The SUBVL encoding value may be thought of as an inclusive range of a
448 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
449 this may be considered to be elements 0b00 to 0b01 inclusive.
451 ## MASK/MASK_SRC & MASKMODE Encoding
453 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
454 types may not be mixed.
456 Special note: to disable predication this field must be set to zero in
457 combination with Integer Predication also being set to 0b000. this has the
458 effect of enabling "all 1s" in the predicate mask, which is equivalent to
459 "not having any predication at all" and consequently, in combination with
460 all other default zeros, fully disables SV (`scalar identity behaviour`).
462 `MASKMODE` may be set to one of 2 values:
464 | Value | Description |
465 |-----------|------------------------------------------------------|
466 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
467 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
469 Integer Twin predication has a second set of 3 bits that uses the same
470 encoding thus allowing either the same register (r3, r10 or r31) to be
471 used for both src and dest, or different regs (one for src, one for dest).
473 Likewise CR based twin predication has a second set of 3 bits, allowing
474 a different test to be applied.
476 Note that it is assumed that Predicate Masks (whether INT or CR) are
477 read *before* the operations proceed. In practice (for CR Fields)
478 this creates an unnecessary block on parallelism. Therefore, it is up
479 to the programmer to ensure that the CR fields used as Predicate Masks
480 are not being written to by any parallel Vector Loop. Doing so results
481 in **UNDEFINED** behaviour, according to the definition outlined in the
482 Power ISA v3.0B Specification.
484 Hardware Implementations are therefore free and clear to delay reading
485 of individual CR fields until the actual predicated element operation
486 needs to take place, safe in the knowledge that no programmer will have
487 issued a Vector Instruction where previous elements could have overwritten
488 (destroyed) not-yet-executed CR-Predicated element operations.
490 ### Integer Predication (MASKMODE=0)
492 When the predicate mode bit is zero the 3 bits are interpreted as below.
493 Twin predication has an identical 3 bit field similarly encoded.
495 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
498 | Value | Mnemonic | Element `i` enabled if: |
499 |-------|----------|------------------------------|
500 | 000 | ALWAYS | predicate effectively all 1s |
501 | 001 | 1 << R3 | `i == R3` |
502 | 010 | R3 | `R3 & (1 << i)` is non-zero |
503 | 011 | ~R3 | `R3 & (1 << i)` is zero |
504 | 100 | R10 | `R10 & (1 << i)` is non-zero |
505 | 101 | ~R10 | `R10 & (1 << i)` is zero |
506 | 110 | R30 | `R30 & (1 << i)` is non-zero |
507 | 111 | ~R30 | `R30 & (1 << i)` is zero |
509 r10 and r30 are at the high end of temporary and unused registers,
510 so as not to interfere with register allocation from ABIs.
512 ### CR-based Predication (MASKMODE=1)
514 When the predicate mode bit is one the 3 bits are interpreted as below.
515 Twin predication has an identical 3 bit field similarly encoded.
517 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
520 | Value | Mnemonic | Element `i` is enabled if |
521 |-------|----------|--------------------------|
522 | 000 | lt | `CR[offs+i].LT` is set |
523 | 001 | nl/ge | `CR[offs+i].LT` is clear |
524 | 010 | gt | `CR[offs+i].GT` is set |
525 | 011 | ng/le | `CR[offs+i].GT` is clear |
526 | 100 | eq | `CR[offs+i].EQ` is set |
527 | 101 | ne | `CR[offs+i].EQ` is clear |
528 | 110 | so/un | `CR[offs+i].FU` is set |
529 | 111 | ns/nu | `CR[offs+i].FU` is clear |
531 CR based predication. TODO: select alternate CR for twin predication? see
532 [[discussion]] Overlap of the two CR based predicates must be taken
533 into account, so the starting point for one of them must be suitably
534 high, or accept that for twin predication VL must not exceed the range
535 where overlap will occur, *or* that they use the same starting point
536 but select different *bits* of the same CRs
538 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised
539 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
541 The CR Predicates chosen must start on a boundary that Vectorised CR
542 operations can access cleanly, in full. With EXTRA2 restricting starting
543 points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
544 CR Predicate Masks have to be adapted to fit on these boundaries as well.
546 ## Extra Remapped Encoding <a name="extra_remap"> </a>
548 Shows all instruction-specific fields in the Remapped Encoding
549 `RM[10:18]` for all instruction variants. Note that due to the very
550 tight space, the encoding mode is *not* included in the prefix itself.
551 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
552 on a per-instruction basis, and, like "Forms" are given a designation
553 (below) of the form `RM-nP-nSnD`. The full list of which instructions
554 use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV
555 files have been provided which will make the task of creating SV-aware
556 ISA decoders easier*).
558 These mappings are part of the SVP64 Specification in exactly the same
559 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
560 will need a corresponding SVP64 Mapping, which can be derived by-rote
561 from examining the Register "Profile" of the instruction.
563 There are two categories: Single and Twin Predication. Due to space
564 considerations further subdivision of Single Predication is based on
565 whether the number of src operands is 2 or 3. With only 9 bits available
566 some compromises have to be made.
568 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
569 instructions (fmadd, isel, madd).
570 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
571 instructions (src1 src2 dest)
572 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
573 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
574 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
578 | Field Name | Field bits | Description |
579 |------------|------------|----------------------------------------|
580 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
581 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
582 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
583 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
584 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
586 These are for 3 operand in and either 1 or 2 out instructions.
587 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
588 such as `maddedu` have an implicit second destination, RS, the
589 selection of which is determined by bit 18.
593 | Field Name | Field bits | Description |
594 |------------|------------|-------------------------------------------|
595 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
596 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
597 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
599 These are for 2 operand 1 dest instructions, such as `add RT, RA,
600 RB`. However also included are unusual instructions with an implicit
601 dest that is identical to its src reg, such as `rlwinmi`.
603 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
604 not have sufficient bit fields to allow an alternative destination.
605 With SV however this becomes possible. Therefore, the fact that the
606 dest is implicitly also a src should not mislead: due to the *prefix*
607 they are different SV regs.
609 * `rlwimi RA, RS, ...`
610 * Rsrc1_EXTRA3 applies to RS as the first src
611 * Rsrc2_EXTRA3 applies to RA as the secomd src
612 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
614 With the addition of the EXTRA bits, the three registers
615 each may be *independently* made vector or scalar, and be independently
616 augmented to 7 bits in length.
620 | Field Name | Field bits | Description |
621 |------------|------------|----------------------------|
622 | Rdest_EXTRA3 | `10:12` | extends Rdest |
623 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
624 | MASK_SRC | `16:18` | Execution Mask for Source |
626 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
630 single-predicate, three registers (2 read, 1 write)
632 | Field Name | Field bits | Description |
633 |------------|------------|----------------------------|
634 | Rdest_EXTRA3 | `10:12` | extends Rdest |
635 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
636 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
638 ### RM-2P-2S1D/1S2D/3S
640 The primary purpose for this encoding is for Twin Predication on LOAD
641 and STORE operations. see [[sv/ldst]] for detailed anslysis.
645 | Field Name | Field bits | Description |
646 |------------|------------|----------------------------|
647 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
648 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
649 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
650 | MASK_SRC | `16:18` | Execution Mask for Source |
652 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
653 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
655 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src:
656 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
658 Note also that LD with update indexed, which takes 2 src and 2 dest
659 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
660 Twin Predication. therefore these are treated as RM-2P-2S1D and the
661 src spec for RA is also used for the same RA as a dest.
663 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
664 or increased latency in some implementations due to lane-crossing.
668 EXTRA is the means by which two things are achieved:
670 1. Registers are marked as either Vector *or Scalar*
671 2. Register field numbers (limited typically to 5 bit)
672 are extended in range, both for Scalar and Vector.
674 The register files are therefore extended:
676 * INT is extended from r0-31 to r0-127
677 * FP is extended from fp0-32 to fp0-fp127
678 * CR Fields are extended from CR0-7 to CR0-127
680 However due to pressure in `RM.EXTRA` not all these registers
681 are accessible by all instructions, particularly those with
682 a large number of operands (`madd`, `isel`).
684 In the following tables register numbers are constructed from the
685 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
686 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
687 designation for a given instruction. The prefixing is arranged so that
688 interoperability between prefixing and nonprefixing of scalar registers
689 is direct and convenient (when the EXTRA field is all zeros).
691 A pseudocode algorithm explains the relationship, for INT/FP (see
692 SVP64 appendix for CRs)
698 spec = EXTRA2 << 1 # same as EXTRA3, shifted
700 return (RA << 2) | spec[1:2]
702 return (spec[1:2] << 5) | RA
705 Future versions may extend to 256 by shifting Vector numbering up.
706 Scalar will not be altered.
708 Note that in some cases the range of starting points for Vectors
713 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
716 Fields are as follows:
719 * Mode: register is tagged as scalar or vector
720 * Range/Inc: the range of registers accessible from this EXTRA
721 encoding, and the "increment" (accessibility). "/4" means
722 that this EXTRA encoding may only give access (starting point)
724 * MSB..LSB: the bit field showing how the register opcode field
725 combines with EXTRA to give (extend) the register number (GPR)
727 | Value | Mode | Range/Inc | 6..0 |
728 |-----------|-------|---------------|---------------------|
729 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
730 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
731 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
732 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
733 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
734 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
735 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
736 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
740 If EXTRA2 is zero will map to
741 "scalar identity behaviour" i.e Scalar Power ISA register naming:
743 | Value | Mode | Range/inc | 6..0 |
744 |----------|-------|---------------|-----------|
745 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
746 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
747 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
748 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
750 **Note that unlike in EXTRA3, in EXTRA2**:
752 * the GPR Vectors may only start from
753 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
754 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
756 as there is insufficient bits to cover the full range.
760 CR Field encoding is essentially the same but made more complex due to CRs
761 being bit-based, because the application of SVP64 element-numbering applies
762 to the CR *Field* numbering not the CR register *bit* numbering.
763 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
764 and Scalars may only go from `CR0, CR1, ... CR31`
766 Encoding shown MSB down to LSB
768 For a 5-bit operand (BA, BB, BT):
770 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
771 |-------|------|---------------|-----------| --------|---------|
772 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
773 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
774 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
775 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
776 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
777 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
778 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
779 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
781 For a 3-bit operand (e.g. BFA):
783 | Value | Mode | Range/Inc | 6..3 | 2..0 |
784 |-------|------|---------------|-----------| --------|
785 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
786 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
787 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
788 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
789 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
790 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
791 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
792 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
796 CR encoding is essentially the same but made more complex due to CRs
797 being bit-based, because the application of SVP64 element-numbering applies
798 to the CR *Field* numbering not the CR register *bit* numbering.
799 See separate section for explanation and pseudocode.
800 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
802 Encoding shown MSB down to LSB
804 For a 5-bit operand (BA, BB, BC):
806 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
807 |-------|--------|----------------|---------|---------|---------|
808 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
809 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
810 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
811 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
813 For a 3-bit operand (e.g. BFA):
815 | Value | Mode | Range/Inc | 6..3 | 2..0 |
816 |-------|------|---------------|-----------| --------|
817 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
818 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
819 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
820 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
827 # Normal SVP64 Modes, for Arithmetic and Logical Operations
829 Normal SVP64 Mode covers Arithmetic and Logical operations
830 to provide suitable additional behaviour. The Mode
831 field is bits 19-23 of the [[svp64]] RM Field.
835 Mode is an augmentation of SV behaviour, providing additional
836 functionality. Some of these alterations are element-based (saturation),
837 others involve post-analysis (predicate result) and others are
838 Vector-based (mapreduce, fail-on-first).
840 [[sv/ldst]], [[sv/cr_ops]] and [[sv/branches]] are covered separately:
841 the following Modes apply to Arithmetic and Logical SVP64 operations:
843 * **simple** mode is straight vectorisation. no augmentations: the
844 vector comprises an array of independently created results.
845 * **ffirst** or data-dependent fail-on-first: see separate section.
846 the vector may be truncated depending on certain criteria.
847 *VL is altered as a result*.
848 * **sat mode** or saturation: clamps each element result to a min/max
849 rather than overflows / wraps. allows signed and unsigned clamping
851 * **reduce mode**. if used correctly, a mapreduce (or a prefix sum)
852 is performed. see [[svp64/appendix]].
853 note that there are comprehensive caveats when using this mode.
854 * **pred-result** will test the result (CR testing selects a bit of CR
855 and inverts it, just like branch conditional testing) and if the
856 test fails it is as if the *destination* predicate bit was zero even
857 before starting the operation. When Rc=1 the CR element however is
858 still stored in the CR regfile, even if the test failed. See appendix
861 Note that ffirst and reduce modes are not anticipated to be
862 high-performance in some implementations. ffirst due to interactions
863 with VL, and reduce due to it requiring additional operations to produce
864 a result. simple, saturate and pred-result are however inter-element
865 independent and may easily be parallelised to give high performance,
866 regardless of the value of VL.
868 The Mode table for Arithmetic and Logical operations is laid out as
871 | 0-1 | 2 | 3 4 | description |
872 | --- | --- |---------|-------------------------- |
873 | 00 | 0 | dz sz | simple mode |
874 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce) |
875 | 00 | 1 | 1 / | reserved |
876 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
877 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
878 | 10 | N | dz sz | sat mode: N=0/1 u/s |
879 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
880 | 11 | inv | zz RC1 | Rc=0: pred-result z/nonz |
884 * **sz / dz** if predication is enabled will put zeros into the dest
885 (or as src in the case of twin pred) when the predicate bit is zero.
886 otherwise the element is ignored or skipped, depending on context.
887 * **zz**: both sz and dz are set equal to this flag
888 * **inv CR bit** just as in branches (BO) these bits allow testing of
889 a CR bit and whether it is set (inv=0) or unset (inv=1)
890 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
891 than the normal 0..VL-1
892 * **N** sets signed/unsigned saturation.
893 * **RC1** as if Rc=1, enables access to `VLi`.
894 * **VLi** VL inclusive: in fail-first mode, the truncation of
895 VL *includes* the current element at the failure point rather
896 than excludes it from the count.
898 For LD/ST Modes, see [[sv/ldst]]. For Condition Registers see
899 [[sv/cr_ops]]. For Branch modes, see [[sv/branches]].
901 ## Rounding, clamp and saturate
903 To help ensure for example that audio quality is not compromised by
904 overflow, "saturation" is provided, as well as a way to detect when
905 saturation occurred if desired (Rc=1). When Rc=1 there will be a *vector*
906 of CRs, one CR per element in the result (Note: this is different from
907 VSX which has a single CR per block).
909 When N=0 the result is saturated to within the maximum range of an
910 unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
911 logic applies to FP operations, with the result being saturated to
912 maximum rather than returning INF, and the minimum to +0.0
914 When N=1 the same occurs except that the result is saturated to the min
915 or max of a signed result, and for FP to the min and max value rather
916 than returning +/- INF.
918 When Rc=1, the CR "overflow" bit is set on the CR associated with the
919 element, to indicate whether saturation occurred. Note that due to
920 the hugely detrimental effect it has on parallel processing, XER.SO is
921 **ignored** completely and is **not** brought into play here. The CR
922 overflow bit is therefore simply set to zero if saturation did not occur,
923 and to one if it did. This behaviour (ignoring XER.SO) is actually optional in
924 the SFFS Compliancy Subset: for SVP64 it is made mandatory *but only on
925 Vectorised instructions*.
927 Note also that saturate on operations that set OE=1 must raise an Illegal
928 Instruction due to the conflicting use of the CR.so bit for storing if
929 saturation occurred. Vectorised Integer Operations that produce a Carry-Out (CA,
930 CA32): these two bits will be `UNDEFINED` if saturation is also requested.
932 Note that the operation takes place at the maximum bitwidth (max of
933 src and dest elwidth) and that truncation occurs to the range of the
936 *Programmer's Note: Post-analysis of the Vector of CRs to find out if any
937 given element hit saturation may be done using a mapreduced CR op (cror),
938 or by using the new crrweird instruction with Rc=1, which will transfer
939 the required CR bits to a scalar integer and update CR0, which will allow
940 testing the scalar integer for nonzero. see [[sv/cr_int_predication]].
941 Alternatively, a Data-Dependent Fail-First may be used to truncate the
942 Vector Length to non-saturated elements, greatly increasing the productivity
943 of parallelised inner hot-loops.*
947 Reduction in SVP64 is similar in essence to other Vector Processing ISAs,
948 but leverages the underlying scalar Base v3.0B operations. Thus it is
949 more a convention that the programmer may utilise to give the appearance
950 and effect of a Horizontal Vector Reduction. Due to the unusual decoupling
951 it is also possible to perform prefix-sum (Fibonacci Series) in certain
952 circumstances. Details are in the SVP64 appendix
954 Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
955 As explained in the [[sv/appendix]] Reduce Mode switches off the check
956 which would normally stop looping if the result register is scalar.
957 Thus, the result scalar register, if also used as a source scalar,
958 may be used to perform sequential accumulation. This *deliberately*
959 sets up a chain of Register Hazard Dependencies, whereas Parallel Reduce
960 [[sv/remap]] deliberately issues a Tree-Schedule of operations that may
963 ## Data-dependent Fail-on-first
965 Data-dependent fail-on-first is very different from LD/ST Fail-First
966 (also known as Fault-First) and is actually CR-field-driven.
967 Vector elements are required to appear
968 to be executed in sequential Program Order. When REMAP is not active,
969 element 0 would be the first.
971 Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
972 CR-creating operation produces a result (including cmp). Similar to
973 branch, an analysis of the CR is performed and if the test fails, the
974 vector operation terminates and discards all element operations **at and
975 above the current one**, and VL is truncated to either the *previous*
976 element or the current one, depending on whether VLi (VL "inclusive")
977 is clear or set, respectively.
979 Thus the new VL comprises a contiguous vector of results, all of which
980 pass the testing criteria (equal to zero, less than zero etc as defined
983 *Note: when VLi is clear, the behaviour at first seems counter-intuitive.
984 A result is calculated but if the test fails it is prohibited from being
985 actually written. This becomes intuitive again when it is remembered
986 that the length that VL is set to is the number of *written* elements, and
987 only when VLI is set will the current element be included in that count.*
989 The CR-based data-driven fail-on-first is "new" and not found in ARM SVE
990 or RVV. At the same time it is "old" because it is almost identical to
991 a generalised form of Z80's `CPIR` instruction. It is extremely useful
992 for reducing instruction count, however requires speculative execution
993 involving modifications of VL to get high performance implementations.
994 An additional mode (RC1=1) effectively turns what would otherwise be an
995 arithmetic operation into a type of `cmp`. The CR is stored (and the
996 CR.eq bit tested against the `inv` field). If the CR.eq bit is equal to
997 `inv` then the Vector is truncated and the loop ends.
999 VLi is only available as an option when `Rc=0` (or for instructions
1000 which do not have Rc). When set, the current element is always also
1001 included in the count (the new length that VL will be set to). This may
1002 be useful in combination with "inv" to truncate the Vector to *exclude*
1003 elements that fail a test, or, in the case of implementations of strncpy,
1004 to include the terminating zero.
1006 In CR-based data-driven fail-on-first there is only the option to select
1007 and test one bit of each CR (just as with branch BO). For more complex
1008 tests this may be insufficient. If that is the case, a vectorised crop
1009 such as crand, cror or [[sv/cr_int_predication]] crweirder may be used,
1010 and ffirst applied to the crop instead of to the arithmetic vector. Note
1011 that crops are covered by the [[sv/cr_ops]] Mode format.
1013 *Programmer's note: `VLi` is only accessible in normal operations which in
1014 turn limits the CR field bit-testing to only `EQ/NE`. [[sv/cr_ops]] are
1015 not so limited. Thus it is possible to use for example `sv.cror/ff=gt/vli
1016 *0,*0,*0`, which is not a `nop` because it allows Fail-First Mode to
1017 perform a test and truncate VL.*
1019 *Hardware implementor's note: effective Sequential Program Order must be preserved.
1020 Speculative Execution is perfectly permitted as long as the speculative elements
1021 are held back from writing to register files (kept in Resevation Stations),
1022 until such time as the relevant
1023 CR Field bit(s) has been analysed. All Speculative elements sequentially beyond the
1024 test-failure point **MUST** be cancelled. This is no different from standard
1025 Out-of-Order Execution and the modification effort to efficiently support
1026 Data-Dependent Fail-First within a pre-existing Multi-Issue Out-of-Order Engine
1027 is anticipated to be minimal. In-Order systems on the other hand are expected,
1028 unavoidably, to be low-performance*.
1030 Two extremely important aspects of ffirst are:
1032 * LDST ffirst may never set VL equal to zero. This because on the first
1033 element an exception must be raised "as normal".
1034 * CR-based data-dependent ffirst on the other hand **can** set VL equal
1035 to zero. This is the only means in the entirety of SV that VL may be set
1036 to zero (with the exception of via the SV.STATE SPR). When VL is set
1037 zero due to the first element failing the CR bit-test, all subsequent
1038 vectorised operations are effectively `nops` which is
1039 *precisely the desired and intended behaviour*.
1041 The second crucial aspect, compared to LDST Ffirst:
1043 * LD/ST Failfirst may (beyond the initial first element
1044 conditions) truncate VL for any architecturally suitable reason. Beyond
1045 the first element LD/ST Failfirst is arbitrarily speculative and 100%
1047 * CR-based data-dependent first on the other hand MUST NOT truncate VL
1048 arbitrarily to a length decided by the hardware: VL MUST only be
1049 truncated based explicitly on whether a test fails. This because it is
1050 a precise Deterministic test on which algorithms can and will will rely.
1052 **Floating-point Exceptions**
1054 When Floating-point exceptions are enabled VL must be truncated at
1055 the point where the Exception appears not to have occurred. If `VLi`
1056 is set then VL must include the faulting element, and thus the faulting
1057 element will always raise its exception. If however `VLi` is clear then
1058 VL **excludes** the faulting element and thus the exception will **never**
1061 Although very strongly discouraged the Exception Mode that permits
1062 Floating Point Exception notification to arrive too late to unwind
1063 is permitted (under protest, due it violating the otherwise 100%
1064 Deterministic nature of Data-dependent Fail-first) and is `UNDEFINED`
1067 **Use of lax FP Exception Notification Mode could result in parallel
1068 computations proceeding with invalid results that have to be explicitly
1069 detected, whereas with the strict FP Execption Mode enabled, FFirst
1070 truncates VL, allows subsequent parallel computation to avoid the
1071 exceptions entirely**
1073 ## Data-dependent fail-first on CR operations (crand etc)
1075 Operations that actually produce or alter CR Field as a result have
1076 their own SVP64 Mode, described in [[sv/cr_ops]].
1080 This mode merges common CR testing with predication, saving on instruction
1081 count. Below is the pseudocode excluding predicate zeroing and elwidth
1082 overrides. Note that the pseudocode for SVP64 CR-ops is slightly different.
1086 # predication test, skip all masked out elements.
1087 if predicate_masked_out(i):
1089 result = op(iregs[RA+i], iregs[RB+i])
1090 CRnew = analyse(result) # calculates eq/lt/gt
1091 # Rc=1 always stores the CR field
1093 CR.field[offs+i] = CRnew
1094 # now test CR, similar to branch
1095 if RC1 or CR.field[BO[0:1]] != BO[2]:
1096 continue # test failed: cancel store
1097 # result optionally stored but CR always is
1098 iregs[RT+i] = result
1101 The reason for allowing the CR element to be stored is so that
1102 post-analysis of the CR Vector may be carried out. For example:
1103 Saturation may have occurred (and been prevented from updating, by the
1104 test) but it is desirable to know *which* elements fail saturation.
1106 Note that RC1 Mode basically turns all operations into `cmp`. The
1107 calculation is performed but it is only the CR that is written. The
1108 element result is *always* discarded, never written (just like `cmp`).
1110 Note that predication is still respected: predicate zeroing is slightly
1111 different: elements that fail the CR test *or* are masked out are zero'd.
1121 All Vector ISAs dating back fifty years have extensive and comprehensive
1122 Load and Store operations that go far beyond the capabilities of Scalar
1123 RISC and most CISC processors, yet at their heart on an individual element
1124 basis may be found to be no different from RISC Scalar equivalents.
1126 The resource savings from Vector LD/ST are significant and stem
1127 from the fact that one single instruction can trigger a dozen (or in
1128 some microarchitectures such as Cray or NEC SX Aurora) hundreds of
1129 element-level Memory accesses.
1131 Additionally, and simply: if the Arithmetic side of an ISA supports
1132 Vector Operations, then in order to keep the ALUs 100% occupied the
1133 Memory infrastructure (and the ISA itself) correspondingly needs Vector
1134 Memory Operations as well.
1136 Vectorised Load and Store also presents an extra dimension (literally)
1137 which creates scenarios unique to Vector applications, that a Scalar
1138 (and even a SIMD) ISA simply never encounters. SVP64 endeavours to add
1139 the modes typically found in *all* Scalable Vector ISAs, without changing
1140 the behaviour of the underlying Base (Scalar) v3.0B operations in any way.
1144 Vectorisation of Load and Store requires creation, from scalar operations,
1145 a number of different modes:
1147 * **fixed aka "unit" stride** - contiguous sequence with no gaps
1148 * **element strided** - sequential but regularly offset, with gaps
1149 * **vector indexed** - vector of base addresses and vector of offsets
1150 * **Speculative fail-first** - where it makes sense to do so
1151 * **Structure Packing** - covered in SV by [[sv/remap]] and Pack/Unpack Mode.
1153 *Despite being constructed from Scalar LD/ST none of these Modes exist
1154 or make sense in any Scalar ISA. They **only** exist in Vector ISAs*
1156 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
1157 as well as Element-width overrides and Twin-Predication.
1159 Note also that Indexed [[sv/remap]] mode may be applied to both v3.0
1160 LD/ST Immediate instructions *and* v3.0 LD/ST Indexed instructions.
1161 LD/ST-Indexed should not be conflated with Indexed REMAP mode:
1162 clarification is provided below.
1164 **Determining the LD/ST Modes**
1166 A minor complication (caused by the retro-fitting of modern Vector
1167 features to a Scalar ISA) is that certain features do not exactly make
1168 sense or are considered a security risk. Fail-first on Vector Indexed
1169 would allow attackers to probe large numbers of pages from userspace,
1170 where strided fail-first (by creating contiguous sequential LDs) does not.
1172 In addition, reduce mode makes no sense. Realistically we need an
1173 alternative table definition for [[sv/svp64]] `RM.MODE`. The following
1177 * predicate-result (mostly for cache-inhibited LD/ST)
1178 * simple (no augmentation)
1179 * fail-first (where Vector Indexed is banned)
1180 * Signed Effective Address computation (Vector Indexed only)
1182 More than that however it is necessary to fit the usual Vector ISA
1183 capabilities onto both Power ISA LD/ST with immediate and to LD/ST
1184 Indexed. They present subtly different Mode tables, which, due to lack
1185 of space, have the following quirks:
1187 * LD/ST Immediate has no individual control over src/dest zeroing,
1188 whereas LD/ST Indexed does.
1189 * LD/ST Immediate has no Saturated Pack/Unpack (Arithmetic Mode does)
1190 * LD/ST Indexed has no Pack/Unpack (REMAP may be used instead)
1192 ## Format and fields
1194 Fields used in tables below:
1196 * **sz / dz** if predication is enabled will put zeros into the dest
1197 (or as src in the case of twin pred) when the predicate bit is zero.
1198 otherwise the element is ignored or skipped, depending on context.
1199 * **zz**: both sz and dz are set equal to this flag.
1200 * **inv CR bit** just as in branches (BO) these bits allow testing of
1201 a CR bit and whether it is set (inv=0) or unset (inv=1)
1202 * **N** sets signed/unsigned saturation.
1203 * **RC1** as if Rc=1, stores CRs *but not the result*
1204 * **SEA** - Signed Effective Address, if enabled performs sign-extension on
1205 registers that have been reduced due to elwidth overrides
1206 * **PI** - post-increment mode (applies to LD/ST with update only).
1207 the Effective Address utilised is always just RA, i.e. the computation of
1208 EA is stored in RA **after** it is actually used.
1209 * **LF** - Load/Store Fail or Fault First: for any reason Load or Store Vectors
1210 may be truncated to (at least) one element, and VL altered to indicate such.
1214 The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE`
1215 (bits 19:23 of `RM`) is:
1217 | 0-1 | 2 | 3 4 | description |
1218 | --- | --- |---------|--------------------------- |
1219 | 00 | 0 | zz els | simple mode |
1220 | 00 | 1 | PI LF | post-increment and Fault-First |
1221 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1222 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1223 | 10 | N | zz els | sat mode: N=0/1 u/s |
1224 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1225 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1227 The `els` bit is only relevant when `RA.isvec` is clear: this indicates
1228 whether stride is unit or element:
1232 svctx.ldstmode = indexed
1234 svctx.ldstmode = unitstride
1235 elif immediate != 0:
1236 svctx.ldstmode = elementstride
1239 An immediate of zero is a safety-valve to allow `LD-VSPLAT`: in effect
1240 the multiplication of the immediate-offset by zero results in reading from
1241 the exact same memory location, *even with a Vector register*. (Normally
1242 this type of behaviour is reserved for the mapreduce modes)
1244 For `LD-VSPLAT`, on non-cache-inhibited Loads, the read can occur just
1245 the once and be copied, rather than hitting the Data Cache multiple
1246 times with the same memory read at the same location. The benefit of
1247 Cache-inhibited LD-splats is that it allows for memory-mapped peripherals
1248 to have multiple data values read in quick succession and stored in
1249 sequentially numbered registers (but, see Note below).
1251 For non-cache-inhibited ST from a vector source onto a scalar destination:
1252 with the Vector loop effectively creating multiple memory writes to
1253 the same location, we can deduce that the last of these will be the
1254 "successful" one. Thus, implementations are free and clear to optimise
1255 out the overwriting STs, leaving just the last one as the "winner".
1256 Bear in mind that predicate masks will skip some elements (in source
1257 non-zeroing mode). Cache-inhibited ST operations on the other hand
1258 **MUST** write out a Vector source multiple successive times to the exact
1259 same Scalar destination. Just like Cache-inhibited LDs, multiple values
1260 may be written out in quick succession to a memory-mapped peripheral
1261 from sequentially-numbered registers.
1263 Note that any memory location may be Cache-inhibited
1264 (Power ISA v3.1, Book III, 1.6.1, p1033)
1266 *Programmer's Note: an immediate also with a Scalar source as a "VSPLAT"
1267 mode is simply not possible: there are not enough Mode bits. One single
1268 Scalar Load operation may be used instead, followed by any arithmetic
1269 operation (including a simple mv) in "Splat" mode.*
1273 The modes for `RA+RB` indexed version are slightly different
1274 but are the same `RM.MODE` bits (19:23 of `RM`):
1276 | 0-1 | 2 | 3 4 | description |
1277 | --- | --- |---------|-------------------------- |
1278 | 00 | SEA | dz sz | simple mode |
1279 | 01 | SEA | dz sz | Strided (scalar only source) |
1280 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1281 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1282 | 11 | inv | zz RC1 | Rc=0: pred-result z/nonz |
1284 Vector Indexed Strided Mode is qualified as follows:
1286 if mode = 0b01 and !RA.isvec and !RB.isvec:
1287 svctx.ldstmode = elementstride
1289 A summary of the effect of Vectorisation of src or dest:
1292 imm(RA) RT.v RA.v no stride allowed
1293 imm(RA) RT.s RA.v no stride allowed
1294 imm(RA) RT.v RA.s stride-select allowed
1295 imm(RA) RT.s RA.s not vectorised
1296 RA,RB RT.v {RA|RB}.v Standard Indexed
1297 RA,RB RT.s {RA|RB}.v Indexed but single LD (no VSPLAT)
1298 RA,RB RT.v {RA&RB}.s VSPLAT possible. stride selectable
1299 RA,RB RT.s {RA&RB}.s not vectorised (scalar identity)
1302 Signed Effective Address computation is only relevant for Vector Indexed
1303 Mode, when elwidth overrides are applied. The source override applies to
1304 RB, and before adding to RA in order to calculate the Effective Address,
1305 if SEA is set RB is sign-extended from elwidth bits to the full 64 bits.
1306 For other Modes (ffirst, saturate), all EA computation with elwidth
1307 overrides is unsigned.
1309 Note that cache-inhibited LD/ST when VSPLAT is activated will perform
1310 **multiple** LD/ST operations, sequentially. Even with scalar src
1311 a Cache-inhibited LD will read the same memory location *multiple
1312 times*, storing the result in successive Vector destination registers.
1313 This because the cache-inhibit instructions are typically used to read
1314 and write memory-mapped peripherals. If a genuine cache-inhibited
1315 LD-VSPLAT is required then a single *scalar* cache-inhibited LD should
1316 be performed, followed by a VSPLAT-augmented mv, copying the one *scalar*
1317 value into multiple register destinations.
1319 Note also that cache-inhibited VSPLAT with Predicate-result is possible.
1320 This allows for example to issue a massive batch of memory-mapped
1321 peripheral reads, stopping at the first NULL-terminated character and
1322 truncating VL to that point. No branch is needed to issue that large
1323 burst of LDs, which may be valuable in Embedded scenarios.
1325 ## Vectorisation of Scalar Power ISA v3.0B
1327 Scalar Power ISA Load/Store operations may be seen from their
1328 pseudocode to be of the form:
1336 and for immediate variants:
1344 Thus in the first example, the source registers may each be independently
1345 marked as scalar or vector, and likewise the destination; in the second
1346 example only the one source and one dest may be marked as scalar or
1349 Thus we can see that Vector Indexed may be covered, and, as demonstrated
1350 with the pseudocode below, the immediate can be used to give unit
1351 stride or element stride. With there being no way to tell which from
1352 the Power v3.0B Scalar opcode alone, the choice is provided instead by
1356 # LD not VLD! format - ldop RT, immed(RA)
1357 # op_width: lb=1, lh=2, lw=4, ld=8
1358 op_load(RT, RA, op_width, immed, svctx, RAupdate):
1359 ps = get_pred_val(FALSE, RA); # predication on src
1360 pd = get_pred_val(FALSE, RT); # ... AND on dest
1361 for (i=0, j=0, u=0; i < VL && j < VL;):
1362 # skip nonpredicates elements
1363 if (RA.isvec) while (!(ps & 1<<i)) i++;
1364 if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
1365 if (RT.isvec) while (!(pd & 1<<j)) j++;
1367 offs = 0; # added afterwards
1368 if RA.isvec: srcbase = ireg[RA+i]
1369 else srcbase = ireg[RA]
1370 elif svctx.ldstmode == elementstride:
1371 # element stride mode
1373 offs = i * immed # j*immed for a ST
1374 elif svctx.ldstmode == unitstride:
1377 offs = immed + (i * op_width) # j*op_width for ST
1379 # quirky Vector indexed mode but with an immediate
1380 srcbase = ireg[RA+i]
1383 # standard scalar mode (but predicated)
1384 # no stride multiplier means VSPLAT mode
1391 ireg[RT+j] <= MEM[EA];
1392 # check post-increment of EA
1393 if postinc: EA = srcbase + immed;
1395 if RAupdate: ireg[RAupdate+u] = EA;
1397 break # destination scalar, end now
1399 if (RAupdate.isvec) u++;
1406 # format: ldop RT, RA, RB
1407 function op_ldx(RT, RA, RB, RAupdate=False) # LD not VLD!
1408 ps = get_pred_val(FALSE, RA); # predication on src
1409 pd = get_pred_val(FALSE, RT); # ... AND on dest
1410 for (i=0, j=0, k=0, u=0; i < VL && j < VL && k < VL):
1411 # skip nonpredicated RA, RB and RT
1412 if (RA.isvec) while (!(ps & 1<<i)) i++;
1413 if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
1414 if (RB.isvec) while (!(ps & 1<<k)) k++;
1415 if (RT.isvec) while (!(pd & 1<<j)) j++;
1416 if svctx.ldstmode == elementstride:
1417 EA = ireg[RA] + ireg[RB]*j # register-strided
1419 EA = ireg[RA+i] + ireg[RB+k] # indexed address
1420 if RAupdate: ireg[RAupdate+u] = EA
1421 ireg[RT+j] <= MEM[EA];
1423 break # destination scalar, end immediately
1425 if (RAupdate.isvec) u++;
1430 Note that Element-Strided uses the Destination Step because with both
1431 sources being Scalar as a prerequisite condition of activation of
1432 Element-Stride Mode, the source step (being Scalar) would never advance.
1434 Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update"
1435 mode (`ldux`) to be effectively a *completely different* register from
1436 RA-as-a-source. This because there is room in svp64 to extend RA-as-src
1437 as well as RA-as-dest, both independently as scalar or vector *and*
1438 independently extending their range.
1440 *Programmer's note: being able to set RA-as-a-source as separate from
1441 RA-as-a-destination as Scalar is **extremely valuable** once it is
1442 remembered that Simple-V element operations must be in Program Order,
1443 especially in loops, for saving on multiple address computations. Care
1444 does have to be taken however that RA-as-src is not overwritten by
1445 RA-as-dest unless intentionally desired, especially in element-strided
1448 ## LD/ST Indexed vs Indexed REMAP
1450 Unfortunately the word "Indexed" is used twice in completely different
1451 contexts, potentially causing confusion.
1453 * There has existed instructions in the Power ISA `ld RT,RA,RB` since
1454 its creation: these are called "LD/ST Indexed" instructions and their
1455 name and meaning is well-established.
1456 * There now exists, in Simple-V, a REMAP mode called "Indexed"
1457 Mode that can be applied to *any* instruction **including those
1458 named LD/ST Indexed**.
1460 Whilst it may be costly in terms of register reads to allow REMAP Indexed
1461 Mode to be applied to any Vectorised LD/ST Indexed operation such as
1462 `sv.ld *RT,RA,*RB`, or even misleadingly labelled as redundant, firstly
1463 the strict application of the RISC Paradigm that Simple-V follows makes
1464 it awkward to consider *preventing* the application of Indexed REMAP to
1465 such operations, and secondly they are not actually the same at all.
1467 Indexed REMAP, as applied to RB in the instruction `sv.ld *RT,RA,*RB`
1468 effectively performs an *in-place* re-ordering of the offsets, RB.
1469 To achieve the same effect without Indexed REMAP would require taking
1470 a *copy* of the Vector of offsets starting at RB, manually explicitly
1471 reordering them, and finally using the copy of re-ordered offsets in a
1472 non-REMAP'ed `sv.ld`. Using non-strided LD as an example, pseudocode
1473 showing what actually occurs, where the pseudocode for `indexed_remap`
1474 may be found in [[sv/remap]]:
1477 # sv.ld *RT,RA,*RB with Index REMAP applied to RB
1480 rb_idx = indexed_remap(i) # remap
1482 rb_idx = i # use the index as-is
1483 EA = GPR(RA) + GPR(RB+rb_idx)
1484 GPR(RT+i) = MEM(EA, 8)
1487 Thus it can be seen that the use of Indexed REMAP saves copying
1488 and manual reordering of the Vector of RB offsets.
1492 LD/ST ffirst treats the first LD/ST in a vector (element 0 if REMAP
1493 is not active) as an ordinary one, with all behaviour with respect to
1494 Interrupts Exceptions Page Faults Memory Management being identical
1495 in every regard to Scalar v3.0 Power ISA LD/ST. However for elements
1496 1 and above, if an exception would occur, then VL is **truncated**
1497 to the previous element: the exception is **not** then raised because
1498 the LD/ST that would otherwise have caused an exception is *required*
1499 to be cancelled. Additionally an implementor may choose to truncate VL
1500 for any arbitrary reason *except for the very first*.
1502 ffirst LD/ST to multiple pages via a Vectorised Index base is
1503 considered a security risk due to the abuse of probing multiple
1504 pages in rapid succession and getting speculative feedback on which
1505 pages would fail. Therefore Vector Indexed LD/ST is prohibited
1506 entirely, and the Mode bit instead used for element-strided LD/ST.
1509 for(i = 0; i < VL; i++)
1510 reg[rt + i] = mem[reg[ra] + i * reg[rb]];
1513 High security implementations where any kind of speculative probing of
1514 memory pages is considered a risk should take advantage of the fact
1515 that implementations may truncate VL at any point, without requiring
1516 software to be rewritten and made non-portable. Such implementations may
1517 choose to *always* set VL=1 which will have the effect of terminating
1518 any speculative probing (and also adversely affect performance), but
1519 will at least not require applications to be rewritten.
1521 Low-performance simpler hardware implementations may also choose (always)
1522 to also set VL=1 as the bare minimum compliant implementation of LD/ST
1523 Fail-First. It is however critically important to remember that the first
1524 element LD/ST **MUST** be treated as an ordinary LD/ST, i.e. **MUST**
1525 raise exceptions exactly like an ordinary LD/ST.
1527 For ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value
1528 for any implementation-specific reason. For example: it is perfectly
1529 reasonable for implementations to alter VL when ffirst LD or ST operations
1530 are initiated on a nonaligned boundary, such that within a loop the
1531 subsequent iteration of that loop begins the following ffirst LD/ST
1532 operations on an aligned boundary such as the beginning of a cache line,
1533 or beginning of a Virtual Memory page. Likewise, to reduce workloads or
1536 Vertical-First Mode is slightly strange in that only one element at a time
1537 is ever executed anyway. Given that programmers may legitimately choose
1538 to alter srcstep and dststep in non-sequential order as part of explicit
1539 loops, it is neither possible nor safe to make speculative assumptions
1540 about future LD/STs. Therefore, Fail-First LD/ST in Vertical-First is
1541 `UNDEFINED`. This is very different from Arithmetic (Data-dependent)
1542 FFirst where Vertical-First Mode is fully deterministic, not speculative.
1544 ## LOAD/STORE Elwidths <a name="elwidth"></a>
1546 Loads and Stores are almost unique in that the Power Scalar ISA
1547 provides a width for the operation (lb, lh, lw, ld). Only `extsb` and
1548 others like it provide an explicit operation width. There are therefore
1549 *three* widths involved:
1551 * operation width (lb=8, lh=16, lw=32, ld=64)
1552 * src element width override (8/16/32/default)
1553 * destination element width override (8/16/32/default)
1555 Some care is therefore needed to express and make clear the transformations,
1556 which are expressly in this order:
1558 * Calculate the Effective Address from RA at full width
1559 but (on Indexed Load) allow srcwidth overrides on RB
1560 * Load at the operation width (lb/lh/lw/ld) as usual
1561 * byte-reversal as usual
1562 * Non-saturated mode:
1563 - zero-extension or truncation from operation width to dest elwidth
1564 - place result in destination at dest elwidth
1566 - Sign-extension or truncation from operation width to dest width
1567 - signed/unsigned saturation down to dest elwidth
1569 In order to respect Power v3.0B Scalar behaviour the memory side
1570 is treated effectively as completely separate and distinct from SV
1571 augmentation. This is primarily down to quirks surrounding LE/BE and
1574 It is rather unfortunately possible to request an elwidth override on
1575 the memory side which does not mesh with the overridden operation width:
1576 these result in `UNDEFINED` behaviour. The reason is that the effect
1577 of attempting a 64-bit `sv.ld` operation with a source elwidth override
1578 of 8/16/32 would result in overlapping memory requests, particularly
1579 on unit and element strided operations. Thus it is `UNDEFINED` when
1580 the elwidth is smaller than the memory operation width. Examples include
1581 `sv.lw/sw=16/els` which requests (overlapping) 4-byte memory reads offset
1582 from each other at 2-byte intervals. Store likewise is also `UNDEFINED`
1583 where the dest elwidth override is less than the operation width.
1585 Note the following regarding the pseudocode to follow:
1587 * `scalar identity behaviour` SV Context parameter conditions turn this
1588 into a straight absolute fully-compliant Scalar v3.0B LD operation
1589 * `brev` selects whether the operation is the byte-reversed variant (`ldbrx`
1591 * `op_width` specifies the operation width (`lb`, `lh`, `lw`, `ld`) as
1592 a "normal" part of Scalar v3.0B LD
1593 * `imm_offs` specifies the immediate offset `ld r3, imm_offs(r5)`, again
1594 as a "normal" part of Scalar v3.0B LD
1595 * `svctx` specifies the SV Context and includes VL as well as
1596 source and destination elwidth overrides.
1598 Below is the pseudocode for Unit-Strided LD (which includes Vector
1599 capability). Observe in particular that RA, as the base address in both
1600 Immediate and Indexed LD/ST, does not have element-width overriding
1603 Note that predication, predication-zeroing, and other modes except
1604 saturation have all been removed, for clarity and simplicity:
1608 # this covers unit stride mode and a type of vector offset
1609 function op_ld(RT, RA, op_width, imm_offs, svctx)
1610 for (int i = 0, int j = 0; i < svctx.VL && j < svctx.VL):
1611 if not svctx.unit/el-strided:
1612 # strange vector mode, compute 64 bit address which is
1613 # not polymorphic! elwidth hardcoded to 64 here
1614 srcbase = get_polymorphed_reg(RA, 64, i)
1616 # unit / element stride mode, compute 64 bit address
1617 srcbase = get_polymorphed_reg(RA, 64, 0)
1618 # adjust for unit/el-stride
1621 # read the underlying memory
1622 memread <= MEM(srcbase + imm_offs, op_width)
1625 if svpctx.saturation_mode:
1626 # ... saturation adjustment...
1627 memread = clamp(memread, op_width, svctx.dest_elwidth)
1629 # truncate/extend to over-ridden dest width.
1630 memread = adjust_wid(memread, op_width, svctx.dest_elwidth)
1632 # takes care of inserting memory-read (now correctly byteswapped)
1633 # into regfile underlying LE-defined order, into the right place
1634 # within the NEON-like register, respecting destination element
1635 # bitwidth, and the element index (j)
1636 set_polymorphed_reg(RT, svctx.dest_elwidth, j, memread)
1638 # increments both src and dest element indices (no predication here)
1643 Note above that the source elwidth is *not used at all* in LD-immediate.
1645 For LD/Indexed, the key is that in the calculation of the Effective Address,
1646 RA has no elwidth override but RB does. Pseudocode below is simplified
1647 for clarity: predication and all modes except saturation are removed:
1650 # LD not VLD! ld*rx if brev else ld*
1651 function op_ld(RT, RA, RB, op_width, svctx, brev)
1652 for (int i = 0, int j = 0; i < svctx.VL && j < svctx.VL):
1653 if not svctx.el-strided:
1654 # RA not polymorphic! elwidth hardcoded to 64 here
1655 srcbase = get_polymorphed_reg(RA, 64, i)
1657 # element stride mode, again RA not polymorphic
1658 srcbase = get_polymorphed_reg(RA, 64, 0)
1659 # RB *is* polymorphic
1660 offs = get_polymorphed_reg(RB, svctx.src_elwidth, i)
1662 if svctx.SEA: offs = sext(offs, svctx.src_elwidth, 64)
1664 # takes care of (merges) processor LE/BE and ld/ldbrx
1665 bytereverse = brev XNOR MSR.LE
1667 # read the underlying memory
1668 memread <= MEM(srcbase + offs, op_width)
1670 # optionally performs byteswap at op width
1672 memread = byteswap(memread, op_width)
1674 if svpctx.saturation_mode:
1675 # ... saturation adjustment...
1676 memread = clamp(memread, op_width, svctx.dest_elwidth)
1678 # truncate/extend to over-ridden dest width.
1679 memread = adjust_wid(memread, op_width, svctx.dest_elwidth)
1681 # takes care of inserting memory-read (now correctly byteswapped)
1682 # into regfile underlying LE-defined order, into the right place
1683 # within the NEON-like register, respecting destination element
1684 # bitwidth, and the element index (j)
1685 set_polymorphed_reg(RT, svctx.dest_elwidth, j, memread)
1687 # increments both src and dest element indices (no predication here)
1694 In the [[sv/remap]] page the concept of "Remapping" is described. Whilst
1695 it is expensive to set up (2 64-bit opcodes minimum) it provides a way to
1696 arbitrarily perform 1D, 2D and 3D "remapping" of up to 64 elements worth
1697 of LDs or STs. The usual interest in such re-mapping is for example in
1698 separating out 24-bit RGB channel data into separate contiguous registers.
1700 REMAP easily covers this capability, and with dest elwidth overrides
1701 and saturation may do so with built-in conversion that would normally
1702 require additional width-extension, sign-extension and min/max Vectorised
1703 instructions as post-processing stages.
1705 Thus we do not need to provide specialist LD/ST "Structure Packed" opcodes
1706 because the generic abstracted concept of "Remapping", when applied to
1707 LD/ST, will give that same capability, with far more flexibility.
1709 It is worth noting that Pack/Unpack Modes of SVSTATE, which may be
1710 established through `svstep`, are also an easy way to perform regular
1711 Structure Packing, at the vec2/vec3/vec4 granularity level. Beyond that,
1712 REMAP will need to be used.
1718 # Condition Register SVP64 Operations
1720 Condition Register Fields are only 4 bits wide: this presents some
1721 interesting conceptual challenges for SVP64, which was designed
1722 primarily for vectors of arithmetic and logical operations. However
1723 if predicates may be bits of CR Fields it makes sense to extend
1724 Simple-V to cover CR Operations, especially given that Vectorised Rc=1
1725 may be processed by Vectorised CR Operations tbat usefully in turn
1726 may become Predicate Masks to yet more Vector operations, like so:
1729 sv.cmpi/ew=8 *B,*ra,0 # compare bytes against zero
1730 sv.cmpi/ew=8 *B2,*ra,13. # and against newline
1731 sv.cror PM.EQ,B.EQ,B2.EQ # OR compares to create mask
1732 sv.stb/sm=EQ ... # store only nonzero/newline
1735 Element width however is clearly meaningless for a 4-bit collation of
1736 Conditions, EQ LT GE SO. Likewise, arithmetic saturation (an important
1737 part of Arithmetic SVP64) has no meaning. An alternative Mode Format is
1738 required, and given that elwidths are meaningless for CR Fields the bits
1739 in SVP64 `RM` may be used for other purposes.
1741 This alternative mapping **only** applies to instructions that **only**
1742 reference a CR Field or CR bit as the sole exclusive result. This section
1743 **does not** apply to instructions which primarily produce arithmetic
1744 results that also, as an aside, produce a corresponding CR Field (such as
1745 when Rc=1). Instructions that involve Rc=1 are definitively arithmetic
1746 in nature, where the corresponding Condition Register Field can be
1747 considered to be a "co-result". Such CR Field "co-result" arithmeric
1748 operations are firmly out of scope for this section, being covered fully
1751 * Examples of v3.0B instructions to which this section does
1753 - `mfcr` and `cmpi` (3 bit operands) and
1754 - `crnor` and `crand` (5 bit operands).
1755 * Examples to which this section does **not** apply include
1756 `fadds.` and `subf.` which both produce arithmetic results
1757 (and a CR Field co-result).
1759 The CR Mode Format still applies to `sv.cmpi` because despite
1760 taking a GPR as input, the output from the Base Scalar v3.0B `cmpi`
1761 instruction is purely to a Condition Register Field.
1763 Other modes are still applicable and include:
1765 * **Data-dependent fail-first**.
1766 useful to truncate VL based on analysis of a Condition Register result bit.
1768 Reduction is useful for analysing a Vector of Condition Register Fields
1769 and reducing it to one single Condition Register Field.
1771 Predicate-result does not make any sense because when Rc=1 a co-result
1772 is created (a CR Field). Testing the co-result allows the decision to
1773 be made to store or not store the main result, and for CR Ops the CR
1774 Field result *is* the main result.
1778 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
1780 |6 | 7 |19-20| 21 | 22 23 | description |
1781 |--|---|-----| --- |---------|----------------- |
1782 |/ | / |0 RG | 0 | dz sz | simple mode |
1783 |/ | / |0 RG | 1 | dz sz | scalar reduce mode (mapreduce) |
1784 |zz|SNZ|1 VLI| inv | CR-bit | Ffirst 3-bit mode |
1785 |/ |SNZ|1 VLI| inv | dz sz | Ffirst 5-bit mode (implies CR-bit from result) |
1789 * **sz / dz** if predication is enabled will put zeros into the dest
1790 (or as src in the case of twin pred) when the predicate bit is zero.
1791 otherwise the element is ignored or skipped, depending on context.
1792 * **zz** set both sz and dz equal to this flag
1793 * **SNZ** In fail-first mode, on the bit being tested, when sz=1 and
1794 SNZ=1 a value "1" is put in place of "0".
1795 * **inv CR-bit** just as in branches (BO) these bits allow testing of
1796 a CR bit and whether it is set (inv=0) or unset (inv=1)
1797 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
1798 than the normal 0..VL-1
1799 * **SVM** sets "subvector" reduce mode
1800 * **VLi** VL inclusive: in fail-first mode, the truncation of
1801 VL *includes* the current element at the failure point rather
1802 than excludes it from the count.
1804 ## Data-dependent fail-first on CR operations
1806 The principle of data-dependent fail-first is that if, during the course
1807 of sequentially evaluating an element's Condition Test, one such test
1808 is encountered which fails, then VL (Vector Length) is truncated (set)
1809 at that point. In the case of Arithmetic SVP64 Operations the Condition
1810 Register Field generated from Rc=1 is used as the basis for the truncation
1811 decision. However with CR-based operations that CR Field result to be
1812 tested is provided *by the operation itself*.
1814 Data-dependent SVP64 Vectorised Operations involving the creation
1815 or modification of a CR can require an extra two bits, which are not
1816 available in the compact space of the SVP64 RM `MODE` Field. With the
1817 concept of element width overrides being meaningless for CR Fields it
1818 is possible to use the `ELWIDTH` field for alternative purposes.
1820 Condition Register based operations such as `sv.mfcr` and `sv.crand`
1821 can thus be made more flexible. However the rules that apply in this
1822 section also apply to future CR-based instructions.
1824 There are two primary different types of CR operations:
1826 * Those which have a 3-bit operand field (referring to a CR Field)
1827 * Those which have a 5-bit operand (referring to a bit within the
1830 Examining these two types it is observed that the difference may
1831 be considered to be that the 5-bit variant *already* provides the
1832 prerequisite information about which CR Field bit (EQ, GE, LT, SO) is
1833 to be operated on by the instruction. Thus, logically, we may set the
1836 * When a 5-bit CR Result field is used in an instruction, the
1837 5-bit variant of Data-Dependent Fail-First
1838 must be used. i.e. the bit of the CR field to be tested is
1839 the one that has just been modified (created) by the operation.
1840 * When a 3-bit CR Result field is used the 3-bit variant
1841 must be used, providing as it does the missing `CRbit` field
1842 in order to select which CR Field bit of the result shall
1843 be tested (EQ, LE, GE, SO)
1845 The reason why the 3-bit CR variant needs the additional CR-bit field
1846 should be obvious from the fact that the 3-bit CR Field from the base
1847 Power ISA v3.0B operation clearly does not contain and is missing the
1848 two CR Field Selector bits. Thus, these two bits (to select EQ, LE,
1849 GE or SO) must be provided in another way.
1851 Examples of the former type:
1853 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
1854 to be tested against `inv` is the one selected by `BT`
1855 * mcrf. This has only 3-bit (BF, BFA). In order to select the
1856 bit to be tested, the alternative encoding must be used.
1857 With `CRbit` coming from the SVP64 RM bits 22-23 the bit
1858 of BF to be tested is identified.
1860 Just as with SVP64 [[sv/branches]] there is the option to truncate
1861 VL to include the element being tested (`VLi=1`) and to exclude it
1864 Also exactly as with [[sv/normal]] fail-first, VL cannot, unlike
1865 [[sv/ldst]], be set to an arbitrary value. Deterministic behaviour
1868 ## Reduction and Iteration
1870 Bearing in mind as described in the svp64 Appendix, SVP64 Horizontal
1871 Reduction is a deterministic schedule on top of base Scalar v3.0
1872 operations, the same rules apply to CR Operations, i.e. that programmers
1873 must follow certain conventions in order for an *end result* of a
1874 reduction to be achieved. Unlike other Vector ISAs *there are no explicit
1875 reduction opcodes* in SVP64: Schedules however achieve the same effect.
1877 Due to these conventions only reduction on operations such as `crand`
1878 and `cror` are meaningful because these have Condition Register Fields
1879 as both input and output. Meaningless operations are not prohibited
1880 because the cost in hardware of doing so is prohibitive, but neither
1881 are they `UNDEFINED`. Implementations are still required to execute them
1882 but are at liberty to optimise out any operations that would ultimately
1883 be overwritten, as long as Strict Program Order is still obvservable by
1886 Also bear in mind that 'Reverse Gear' may be enabled, which can be
1887 used in combination with overlapping CR operations to iteratively
1888 accumulate results. Issuing a `sv.crand` operation for example with
1889 `BA` differing from `BB` by one Condition Register Field would result
1890 in a cascade effect, where the first-encountered CR Field would set the
1891 result to zero, and also all subsequent CR Field elements thereafter:
1894 # sv.crand/mr/rg CR4.ge.v, CR5.ge.v, CR4.ge.v
1895 for i in VL-1 downto 0 # reverse gear
1896 CR.field[4+i].ge &= CR.field[5+i].ge
1899 `sv.crxor` with reduction would be particularly useful for parity
1900 calculation for example, although there are many ways in which the same
1901 calculation could be carried out after transferring a vector of CR Fields
1902 to a GPR using crweird operations.
1904 Implementations are free and clear to optimise these reductions in any way
1905 they see fit, as long as the end-result is compatible with Strict Program
1906 Order being observed, and Interrupt latency is not adversely impacted.
1908 ## Unusual and quirky CR operations
1910 **cmp and other compare ops**
1912 `cmp` and `cmpi` etc take GPRs as sources and create a CR Field as a result.
1917 With `ELWIDTH` applying to the source GPR operands this is perfectly fine.
1919 **crweird operations**
1921 There are 4 weird CR-GPR operations and one reasonable one in
1922 the [[cr_int_predication]] set:
1928 * mcrfm - reasonably normal and referring to CR Fields for src and dest.
1930 The "weird" operations have a non-standard behaviour, being able to
1931 treat *individual bits* of a GPR effectively as elements. They are
1932 expected to be Micro-coded by most Hardware implementations.
1939 # SVP64 Branch Conditional behaviour
1941 Please note: although similar, SVP64 Branch instructions should be
1942 considered completely separate and distinct from standard scalar
1943 OpenPOWER-approved v3.0B branches. **v3.0B branches are in no way
1944 impacted, altered, changed or modified in any way, shape or form by the
1945 SVP64 Vectorised Variants**.
1947 It is also extremely important to note that Branches are the sole
1948 pseudo-exception in SVP64 to `Scalar Identity Behaviour`. SVP64 Branches
1949 contain additional modes that are useful for scalar operations (i.e. even
1950 when VL=1 or when using single-bit predication).
1954 Scalar 3.0B Branch Conditional operations, `bc`, `bctar` etc. test
1955 a Condition Register. However for parallel processing it is simply
1956 impossible to perform multiple independent branches: the Program
1957 Counter simply cannot branch to multiple destinations based on multiple
1958 conditions. The best that can be done is to test multiple Conditions
1959 and make a decision of a *single* branch, based on analysis of a *Vector*
1960 of CR Fields which have just been calculated from a *Vector* of results.
1962 In 3D Shader binaries, which are inherently parallelised and predicated,
1963 testing all or some results and branching based on multiple tests is
1964 extremely common, and a fundamental part of Shader Compilers. Example:
1965 without such multi-condition test-and-branch, if a predicate mask is
1966 all zeros a large batch of instructions may be masked out to `nop`,
1967 and it would waste CPU cycles to run them. 3D GPU ISAs can test for
1968 this scenario and, with the appropriate predicate-analysis instruction,
1969 jump over fully-masked-out operations, by spotting that *all* Conditions
1972 Unless Branches are aware and capable of such analysis, additional
1973 instructions would be required which perform Horizontal Cumulative
1974 analysis of Vectorised Condition Register Fields, in order to reduce
1975 the Vector of CR Fields down to one single yes or no decision that a
1976 Scalar-only v3.0B Branch-Conditional could cope with. Such instructions
1977 would be unavoidable, required, and costly by comparison to a single
1978 Vector-aware Branch. Therefore, in order to be commercially competitive,
1979 `sv.bc` and other Vector-aware Branch Conditional instructions are a
1980 high priority for 3D GPU (and OpenCL-style) workloads.
1982 Given that Power ISA v3.0B is already quite powerful, particularly
1983 the Condition Registers and their interaction with Branches, there are
1984 opportunities to create extremely flexible and compact Vectorised Branch
1985 behaviour. In addition, the side-effects (updating of CTR, truncation
1986 of VL, described below) make it a useful instruction even if the branch
1987 points to the next instruction (no actual branch).
1991 When considering an "array" of branch-tests, there are four
1992 primarily-useful modes: AND, OR, NAND and NOR of all Conditions.
1993 NAND and NOR may be synthesised from AND and OR by inverting `BO[1]`
1994 which just leaves two modes:
1996 * Branch takes place on the **first** CR Field test to succeed
1997 (a Great Big OR of all condition tests). Exit occurs
1998 on the first **successful** test.
1999 * Branch takes place only if **all** CR field tests succeed:
2000 a Great Big AND of all condition tests. Exit occurs
2001 on the first **failed** test.
2003 Early-exit is enacted such that the Vectorised Branch does not
2004 perform needless extra tests, which will help reduce reads on
2005 the Condition Register file.
2007 *Note: Early-exit is **MANDATORY** (required) behaviour. Branches
2008 **MUST** exit at the first sequentially-encountered failure point,
2009 for exactly the same reasons for which it is mandatory in programming
2010 languages doing early-exit: to avoid damaging side-effects and to provide
2011 deterministic behaviour. Speculative testing of Condition Register
2012 Fields is permitted, as is speculative calculation of CTR, as long as,
2013 as usual in any Out-of-Order microarchitecture, that speculative testing
2014 is cancelled should an early-exit occur. i.e. the speculation must be
2015 "precise": Program Order must be preserved*
2017 Also note that when early-exit occurs in Horizontal-first Mode, srcstep,
2018 dststep etc. are all reset, ready to begin looping from the beginning
2019 for the next instruction. However for Vertical-first Mode srcstep
2020 etc. are incremented "as usual" i.e. an early-exit has no special impact,
2021 regardless of whether the branch occurred or not. This can leave srcstep
2022 etc. in what may be considered an unusual state on exit from a loop and
2023 it is up to the programmer to reset srcstep, dststep etc. to known-good
2024 values *(easily achieved with `setvl`)*.
2026 Additional useful behaviour involves two primary Modes (both of which
2027 may be enabled and combined):
2029 * **VLSET Mode**: identical to Data-Dependent Fail-First Mode
2030 for Arithmetic SVP64 operations, with more
2031 flexibility and a close interaction and integration into the
2032 underlying base Scalar v3.0B Branch instruction.
2033 Truncation of VL takes place around the early-exit point.
2034 * **CTR-test Mode**: gives much more flexibility over when and why
2035 CTR is decremented, including options to decrement if a Condition
2036 test succeeds *or if it fails*.
2038 With these side-effects, basic Boolean Logic Analysis advises that it
2039 is important to provide a means to enact them each based on whether
2040 testing succeeds *or fails*. This results in a not-insignificant number
2041 of additional Mode Augmentation bits, accompanying VLSET and CTR-test
2044 Predicate skipping or zeroing may, as usual with SVP64, be controlled by
2045 `sz`. Where the predicate is masked out and zeroing is enabled, then in
2046 such circumstances the same Boolean Logic Analysis dictates that rather
2047 than testing only against zero, the option to test against one is also
2048 prudent. This introduces a new immediate field, `SNZ`, which works in
2049 conjunction with `sz`.
2051 Vectorised Branches can be used in either SVP64 Horizontal-First or
2052 Vertical-First Mode. Essentially, at an element level, the behaviour
2053 is identical in both Modes, although the `ALL` bit is meaningless in
2054 Vertical-First Mode.
2056 It is also important to bear in mind that, fundamentally, Vectorised
2057 Branch-Conditional is still extremely close to the Scalar v3.0B
2058 Branch-Conditional instructions, and that the same v3.0B Scalar
2059 Branch-Conditional instructions are still *completely separate and
2060 independent*, being unaltered and unaffected by their SVP64 variants in
2061 every conceivable way.
2063 *Programming note: One important point is that SVP64 instructions are
2064 64 bit. (8 bytes not 4). This needs to be taken into consideration
2065 when computing branch offsets: the offset is relative to the start of
2066 the instruction, which **includes** the SVP64 Prefix*
2068 ## Format and fields
2070 With element-width overrides being meaningless for Condition Register
2071 Fields, bits 4 thru 7 of SVP64 RM may be used for additional Mode bits.
2073 SVP64 RM `MODE` (includes repurposing `ELWIDTH` bits 4:5, and
2074 `ELWIDTH_SRC` bits 6-7 for *alternate* uses) for Branch Conditional:
2076 | 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 | 21 | 22 23 | description |
2077 | - | - | - | - | -- | -- | -- | -- | --- |--------|----------------- |
2078 |ALL|SNZ| / | / | SL |SLu | 0 | 0 | / | LRu sz | simple mode |
2079 |ALL|SNZ| / |VSb| SL |SLu | 0 | 1 | VLI | LRu sz | VLSET mode |
2080 |ALL|SNZ|CTi| / | SL |SLu | 1 | 0 | / | LRu sz | CTR-test mode |
2081 |ALL|SNZ|CTi|VSb| SL |SLu | 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode |
2083 Brief description of fields:
2085 * **sz=1** if predication is enabled and `sz=1` and a predicate
2086 element bit is zero, `SNZ` will
2087 be substituted in place of the CR bit selected by `BI`,
2088 as the Condition tested.
2090 normal SVP64 `sz=1` behaviour, where *only* a zero is put in
2091 place of masked-out predicate bits.
2092 * **sz=0** When `sz=0` skipping occurs as usual on
2093 masked-out elements, but unlike all
2094 other SVP64 behaviour which entirely skips an element with
2095 no related side-effects at all, there are certain
2096 special circumstances where CTR
2097 may be decremented. See CTR-test Mode, below.
2098 * **ALL** when set, all branch conditional tests must pass in order for
2099 the branch to succeed. When clear, it is the first sequentially
2100 encountered successful test that causes the branch to succeed.
2101 This is identical behaviour to how programming languages perform
2102 early-exit on Boolean Logic chains.
2103 * **VLI** VLSET is identical to Data-dependent Fail-First mode.
2104 In VLSET mode, VL *may* (depending on `VSb`) be truncated.
2105 If VLI (Vector Length Inclusive) is clear,
2106 VL is truncated to *exclude* the current element, otherwise it is
2107 included. SVSTATE.MVL is not altered: only VL.
2108 * **SL** identical to `LR` except applicable to SVSTATE. If `SL`
2109 is set, SVSTATE is transferred to SVLR (conditionally on
2110 whether `SLu` is set).
2111 * **SLu**: SVSTATE Link Update, like `LRu` except applies to SVSTATE.
2112 * **LRu**: Link Register Update, used in conjunction with LK=1
2113 to make LR update conditional
2114 * **VSb** In VLSET Mode, after testing,
2115 if VSb is set, VL is truncated if the test succeeds. If VSb is clear,
2116 VL is truncated if a test *fails*. Masked-out (skipped)
2117 bits are not considered
2118 part of testing when `sz=0`
2119 * **CTi** CTR inversion. CTR-test Mode normally decrements per element
2120 tested. CTR inversion decrements if a test *fails*. Only relevant
2123 LRu and CTR-test modes are where SVP64 Branches subtly differ from
2124 Scalar v3.0B Branches. `sv.bcl` for example will always update LR,
2125 whereas `sv.bcl/lru` will only update LR if the branch succeeds.
2127 Of special interest is that when using ALL Mode (Great Big AND of all
2128 Condition Tests), if `VL=0`, which is rare but can occur in Data-Dependent
2129 Modes, the Branch will always take place because there will be no failing
2130 Condition Tests to prevent it. Likewise when not using ALL Mode (Great
2131 Big OR of all Condition Tests) and `VL=0` the Branch is guaranteed not
2132 to occur because there will be no *successful* Condition Tests to make
2135 ## Vectorised CR Field numbering, and Scalar behaviour
2137 It is important to keep in mind that just like all SVP64 instructions,
2138 the `BI` field of the base v3.0B Branch Conditional instruction may be
2139 extended by SVP64 EXTRA augmentation, as well as be marked as either
2140 Scalar or Vector. It is also crucially important to keep in mind that for
2141 CRs, SVP64 sequentially increments the CR *Field* numbers. CR *Fields*
2142 are treated as elements, not bit-numbers of the CR *register*.
2144 The `BI` operand of Branch Conditional operations is five bits, in scalar
2145 v3.0B this would select one bit of the 32 bit CR, comprising eight CR
2146 Fields of 4 bits each. In SVP64 there are 16 32 bit CRs, containing
2147 128 4-bit CR Fields. Therefore, the 2 LSBs of `BI` select the bit from
2148 the CR Field (EQ LT GT SO), and the top 3 bits are extended to either
2149 scalar or vector and to select CR Fields 0..127 as specified in SVP64
2150 [[sv/svp64/appendix]].
2152 When the CR Fields selected by SVP64-Augmented `BI` is marked as scalar,
2153 then as the usual SVP64 rules apply: the Vector loop ends at the first
2154 element tested (the first CR *Field*), after taking predication into
2155 consideration. Thus, also as usual, when a predicate mask is given, and
2156 `BI` marked as scalar, and `sz` is zero, srcstep skips forward to the
2157 first non-zero predicated element, and only that one element is tested.
2159 In other words, the fact that this is a Branch Operation (instead of an
2160 arithmetic one) does not result, ultimately, in significant changes as
2161 to how SVP64 is fundamentally applied, except with respect to:
2163 * the unique properties associated with conditionally
2164 changing the Program Counter (aka "a Branch"), resulting in early-out
2168 Both are outlined below, in later sections.
2170 ## Horizontal-First and Vertical-First Modes
2172 In SVP64 Horizontal-First Mode, the first failure in ALL mode (Great Big
2173 AND) results in early exit: no more updates to CTR occur (if requested);
2174 no branch occurs, and LR is not updated (if requested). Likewise for
2175 non-ALL mode (Great Big Or) on first success early exit also occurs,
2176 however this time with the Branch proceeding. In both cases the testing
2177 of the Vector of CRs should be done in linear sequential order (or in
2178 REMAP re-sequenced order): such that tests that are sequentially beyond
2179 the exit point are *not* carried out. (*Note: it is standard practice
2180 in Programming languages to exit early from conditional tests, however a
2181 little unusual to consider in an ISA that is designed for Parallel Vector
2182 Processing. The reason is to have strictly-defined guaranteed behaviour*)
2184 In Vertical-First Mode, setting the `ALL` bit results in `UNDEFINED`
2185 behaviour. Given that only one element is being tested at a time in
2186 Vertical-First Mode, a test designed to be done on multiple bits is
2189 ## Description and Modes
2191 Predication in both INT and CR modes may be applied to `sv.bc` and other
2192 SVP64 Branch Conditional operations, exactly as they may be applied to
2193 other SVP64 operations. When `sz` is zero, any masked-out Branch-element
2194 operations are not included in condition testing, exactly like all other
2195 SVP64 operations, *including* side-effects such as potentially updating
2196 LR or CTR, which will also be skipped. There is *one* exception here,
2197 which is when `BO[2]=0, sz=0, CTR-test=0, CTi=1` and the relevant element
2198 predicate mask bit is also zero: under these special circumstances CTR
2199 will also decrement.
2201 When `sz` is non-zero, this normally requests insertion of a zero in
2202 place of the input data, when the relevant predicate mask bit is zero.
2203 This would mean that a zero is inserted in place of `CR[BI+32]` for
2204 testing against `BO`, which may not be desirable in all circumstances.
2205 Therefore, an extra field is provided `SNZ`, which, if set, will insert
2206 a **one** in place of a masked-out element, instead of a zero.
2208 (*Note: Both options are provided because it is useful to deliberately
2209 cause the Branch-Conditional Vector testing to fail at a specific point,
2210 controlled by the Predicate mask. This is particularly useful in `VLSET`
2211 mode, which will truncate SVSTATE.VL at the point of the first failed
2214 Normally, CTR mode will decrement once per Condition Test, resulting under
2215 normal circumstances that CTR reduces by up to VL in Horizontal-First
2216 Mode. Just as when v3.0B Branch-Conditional saves at least one instruction
2217 on tight inner loops through auto-decrementation of CTR, likewise it
2218 is also possible to save instruction count for SVP64 loops in both
2219 Vertical-First and Horizontal-First Mode, particularly in circumstances
2220 where there is conditional interaction between the element computation
2221 and testing, and the continuation (or otherwise) of a given loop. The
2222 potential combinations of interactions is why CTR testing options have
2225 Also, the unconditional bit `BO[0]` is still relevant when Predication
2226 is applied to the Branch because in `ALL` mode all nonmasked bits have
2227 to be tested, and when `sz=0` skipping occurs. Even when VLSET mode is
2228 not used, CTR may still be decremented by the total number of nonmasked
2229 elements, acting in effect as either a popcount or cntlz depending
2230 on which mode bits are set. In short, Vectorised Branch becomes an
2231 extremely powerful tool.
2233 **Micro-Architectural Implementation Note**: *when implemented on top
2234 of a Multi-Issue Out-of-Order Engine it is possible to pass a copy of
2235 the predicate and the prerequisite CR Fields to all Branch Units, as
2236 well as the current value of CTR at the time of multi-issue, and for
2237 each Branch Unit to compute how many times CTR would be subtracted,
2238 in a fully-deterministic and parallel fashion. A SIMD-based Branch
2239 Unit, receiving and processing multiple CR Fields covered by multiple
2240 predicate bits, would do the exact same thing. Obviously, however, if
2241 CTR is modified within any given loop (mtctr) the behaviour of CTR is
2242 no longer deterministic.*
2244 ### Link Register Update
2246 For a Scalar Branch, unconditional updating of the Link Register LR
2247 is useful and practical. However, if a loop of CR Fields is tested,
2248 unconditional updating of LR becomes problematic.
2250 For example when using `bclr` with `LRu=1,LK=0` in Horizontal-First Mode,
2251 LR's value will be unconditionally overwritten after the first element,
2252 such that for execution (testing) of the second element, LR has the value
2253 `CIA+8`. This is covered in the `bclrl` example, in a later section.
2255 The addition of a LRu bit modifies behaviour in conjunction with LK,
2258 * `sv.bc` When LRu=0,LK=0, Link Register is not updated
2259 * `sv.bcl` When LRu=0,LK=1, Link Register is updated unconditionally
2260 * `sv.bcl/lru` When LRu=1,LK=1, Link Register will
2261 only be updated if the Branch Condition fails.
2262 * `sv.bc/lru` When LRu=1,LK=0, Link Register will only be updated if
2263 the Branch Condition succeeds.
2265 This avoids destruction of LR during loops (particularly Vertical-First
2268 **SVLR and SVSTATE**
2270 For precisely the reasons why `LK=1` was added originally to the Power
2271 ISA, with SVSTATE being a peer of the Program Counter it becomes necessary
2272 to also add an SVLR (SVSTATE Link Register) and corresponding control bits
2277 Where a standard Scalar v3.0B branch unconditionally decrements CTR when
2278 `BO[2]` is clear, CTR-test Mode introduces more flexibility which allows
2279 CTR to be used for many more types of Vector loops constructs.
2281 CTR-test mode and CTi interaction is as follows: note that `BO[2]`
2282 is still required to be clear for CTR decrements to be considered,
2283 exactly as is the case in Scalar Power ISA v3.0B
2285 * **CTR-test=0, CTi=0**: CTR decrements on a per-element basis
2286 if `BO[2]` is zero. Masked-out elements when `sz=0` are
2287 skipped (i.e. CTR is *not* decremented when the predicate
2288 bit is zero and `sz=0`).
2289 * **CTR-test=0, CTi=1**: CTR decrements on a per-element basis
2290 if `BO[2]` is zero and a masked-out element is skipped
2291 (`sz=0` and predicate bit is zero). This one special case is the
2292 **opposite** of other combinations, as well as being
2293 completely different from normal SVP64 `sz=0` behaviour)
2294 * **CTR-test=1, CTi=0**: CTR decrements on a per-element basis
2295 if `BO[2]` is zero and the Condition Test succeeds.
2296 Masked-out elements when `sz=0` are skipped (including
2297 not decrementing CTR)
2298 * **CTR-test=1, CTi=1**: CTR decrements on a per-element basis
2299 if `BO[2]` is zero and the Condition Test *fails*.
2300 Masked-out elements when `sz=0` are skipped (including
2301 not decrementing CTR)
2303 `CTR-test=0, CTi=1, sz=0` requires special emphasis because it is the
2304 only time in the entirety of SVP64 that has side-effects when
2305 a predicate mask bit is clear. **All** other SVP64 operations
2306 entirely skip an element when sz=0 and a predicate mask bit is zero.
2307 It is also critical to emphasise that in this unusual mode,
2308 no other side-effects occur: **only** CTR is decremented, i.e. the
2309 rest of the Branch operation is skipped.
2313 VLSET Mode truncates the Vector Length so that subsequent instructions
2314 operate on a reduced Vector Length. This is similar to Data-dependent
2315 Fail-First and LD/ST Fail-First, where for VLSET the truncation occurs
2316 at the Branch decision-point.
2318 Interestingly, due to the side-effects of `VLSET` mode it is actually
2319 useful to use Branch Conditional even to perform no actual branch
2320 operation, i.e to point to the instruction after the branch. Truncation of
2321 VL would thus conditionally occur yet control flow alteration would not.
2323 `VLSET` mode with Vertical-First is particularly unusual. Vertical-First
2324 is designed to be used for explicit looping, where an explicit call to
2325 `svstep` is required to move both srcstep and dststep on to the next
2326 element, until VL (or other condition) is reached. Vertical-First Looping
2327 is expected (required) to terminate if the end of the Vector, VL, is
2328 reached. If however that loop is terminated early because VL is truncated,
2329 VLSET with Vertical-First becomes meaningless. Resolving this would
2330 require two branches: one Conditional, the other branching unconditionally
2331 to create the loop, where the Conditional one jumps over it.
2333 Therefore, with `VSb`, the option to decide whether truncation should
2334 occur if the branch succeeds *or* if the branch condition fails allows
2335 for the flexibility required. This allows a Vertical-First Branch to
2336 *either* be used as a branch-back (loop) *or* as part of a conditional
2337 exit or function call from *inside* a loop, and for VLSET to be integrated
2338 into both types of decision-making.
2340 In the case of a Vertical-First branch-back (loop), with `VSb=0` the
2341 branch takes place if success conditions are met, but on exit from that
2342 loop (branch condition fails), VL will be truncated. This is extremely
2345 `VLSET` mode with Horizontal-First when `VSb=0` is still useful, because
2346 it can be used to truncate VL to the first predicated (non-masked-out)
2349 The truncation point for VL, when VLi is clear, must not include skipped
2350 elements that preceded the current element being tested. Example:
2351 `sz=0, VLi=0, predicate mask = 0b110010` and the Condition Register
2352 failure point is at CR Field element 4.
2354 * Testing at element 0 is skipped because its predicate bit is zero
2355 * Testing at element 1 passed
2356 * Testing elements 2 and 3 are skipped because their
2357 respective predicate mask bits are zero
2358 * Testing element 4 fails therefore VL is truncated to **2**
2359 not 4 due to elements 2 and 3 being skipped.
2361 If `sz=1` in the above example *then* VL would have been set to 4 because
2362 in non-zeroing mode the zero'd elements are still effectively part of the
2363 Vector (with their respective elements set to `SNZ`)
2365 If `VLI=1` then VL would be set to 5 regardless of sz, due to being inclusive
2366 of the element actually being tested.
2368 ### VLSET and CTR-test combined
2370 If both CTR-test and VLSET Modes are requested, it is important to
2371 observe the correct order. What occurs depends on whether VLi is enabled,
2372 because VLi affects the length, VL.
2374 If VLi (VL truncate inclusive) is set:
2376 1. compute the test including whether CTR triggers
2377 2. (optionally) decrement CTR
2378 3. (optionally) truncate VL (VSb inverts the decision)
2379 4. decide (based on step 1) whether to terminate looping
2380 (including not executing step 5)
2381 5. decide whether to branch.
2383 If VLi is clear, then when a test fails that element
2384 and any following it
2385 should **not** be considered part of the Vector. Consequently:
2387 1. compute the branch test including whether CTR triggers
2388 2. if the test fails against VSb, truncate VL to the *previous*
2389 element, and terminate looping. No further steps executed.
2390 3. (optionally) decrement CTR
2391 4. decide whether to branch.
2393 ## Boolean Logic combinations
2395 In a Scalar ISA, Branch-Conditional testing even of vector results may be
2396 performed through inversion of tests. NOR of all tests may be performed
2397 by inversion of the scalar condition and branching *out* from the scalar
2398 loop around elements, using scalar operations.
2400 In a parallel (Vector) ISA it is the ISA itself which must perform
2401 the prerequisite logic manipulation. Thus for SVP64 there are an
2402 extraordinary number of nesessary combinations which provide completely
2403 different and useful behaviour. Available options to combine:
2405 * `BO[0]` to make an unconditional branch would seem irrelevant if
2406 it were not for predication and for side-effects (CTR Mode
2408 * Enabling CTR-test Mode and setting `BO[2]` can still result in the
2410 taking place, not because the Condition Test itself failed, but
2411 because CTR reached zero **because**, as required by CTR-test mode,
2412 CTR was decremented as a **result** of Condition Tests failing.
2413 * `BO[1]` to select whether the CR bit being tested is zero or nonzero
2414 * `R30` and `~R30` and other predicate mask options including CR and
2415 inverted CR bit testing
2416 * `sz` and `SNZ` to insert either zeros or ones in place of masked-out
2418 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
2419 `OR` of all tests, respectively.
2420 * Predicate Mask bits, which combine in effect with the CR being
2422 * Inversion of Predicate Masks (`~r3` instead of `r3`, or using
2423 `NE` rather than `EQ`) which results in an additional
2424 level of possible ANDing, ORing etc. that would otherwise
2425 need explicit instructions.
2427 The most obviously useful combinations here are to set `BO[1]` to zero
2428 in order to turn `ALL` into Great-Big-NAND and `ANY` into Great-Big-NOR.
2429 Other Mode bits which perform behavioural inversion then have to work
2430 round the fact that the Condition Testing is NOR or NAND. The alternative
2431 to not having additional behavioural inversion (`SNZ`, `VSb`, `CTi`)
2432 would be to have a second (unconditional) branch directly after the first,
2433 which the first branch jumps over. This contrivance is avoided by the
2434 behavioural inversion bits.
2436 ## Pseudocode and examples
2438 Please see the SVP64 appendix regarding CR bit ordering and for
2439 the definition of `CR{n}`
2441 For comparative purposes this is a copy of the v3.0B `bc` pseudocode
2444 if (mode_is_64bit) then M <- 0
2446 if ¬BO[2] then CTR <- CTR - 1
2447 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2448 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2449 if ctr_ok & cond_ok then
2450 if AA then NIA <-iea EXTS(BD || 0b00)
2451 else NIA <-iea CIA + EXTS(BD || 0b00)
2452 if LK then LR <-iea CIA + 4
2455 Simplified pseudocode including LRu and CTR skipping, which illustrates
2456 clearly that SVP64 Scalar Branches (VL=1) are **not** identical to
2457 v3.0B Scalar Branches. The key areas where differences occur are the
2458 inclusion of predication (which can still be used when VL=1), in when and
2459 why CTR is decremented (CTRtest Mode) and whether LR is updated (which
2460 is unconditional in v3.0B when LK=1, and conditional in SVP64 when LRu=1).
2462 Inline comments highlight the fact that the Scalar Branch behaviour and
2463 pseudocode is still clearly visible and embedded within the Vectorised
2467 if (mode_is_64bit) then M <- 0
2469 # the bit of CR to test, if the predicate bit is zero,
2472 if ¬predicate_bit then testbit = SVRMmode.SNZ
2473 # otherwise apart from the override ctr_ok and cond_ok
2474 # are exactly the same
2475 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2476 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2477 if ¬predicate_bit & ¬SVRMmode.sz then
2478 # this is entirely new: CTR-test mode still decrements CTR
2479 # even when predicate-bits are zero
2480 if ¬BO[2] & CTRtest & ¬CTi then
2482 # instruction finishes here
2484 # usual BO[2] CTR-mode now under CTR-test mode as well
2485 if ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) then CTR <- CTR - 1
2486 # new VLset mode, conditional test truncates VL
2487 if VLSET and VSb = (cond_ok & ctr_ok) then
2488 if SVRMmode.VLI then SVSTATE.VL = srcstep+1
2489 else SVSTATE.VL = srcstep
2490 # usual LR is now conditional, but also joined by SVLR
2492 svlr_ok <- SVRMmode.SL
2493 if ctr_ok & cond_ok then
2494 if AA then NIA <-iea EXTS(BD || 0b00)
2495 else NIA <-iea CIA + EXTS(BD || 0b00)
2496 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2497 if SVRMmode.SLu then svlr_ok <- ¬svlr_ok
2498 if lr_ok then LR <-iea CIA + 4
2499 if svlr_ok then SVLR <- SVSTATE
2502 Below is the pseudocode for SVP64 Branches, which is a little less
2503 obvious but identical to the above. The lack of obviousness is down to
2504 the early-exit opportunities.
2506 Effective pseudocode for Horizontal-First Mode:
2509 if (mode_is_64bit) then M <- 0
2511 cond_ok = not SVRMmode.ALL
2512 for srcstep in range(VL):
2513 # select predicate bit or zero/one
2514 if predicate[srcstep]:
2515 # get SVP64 extended CR field 0..127
2516 SVCRf = SVP64EXTRA(BI>>2)
2518 testbit = CRbits[BI & 0b11]
2519 # testbit = CR[BI+32+srcstep*4]
2520 else if not SVRMmode.sz:
2521 # inverted CTR test skip mode
2522 if ¬BO[2] & CTRtest & ¬CTI then
2524 continue # skip to next element
2526 testbit = SVRMmode.SNZ
2527 # actual element test here
2528 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2529 el_cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2530 # check if CTR dec should occur
2532 if CTRtest & (el_cond_ok ^ CTi) then
2534 if ctrdec then CTR <- CTR - 1
2537 cond_ok &= (el_cond_ok & ctr_ok)
2539 cond_ok |= (el_cond_ok & ctr_ok)
2540 # test for VL to be set (and exit)
2541 if VLSET and VSb = (el_cond_ok & ctr_ok) then
2542 if SVRMmode.VLI then SVSTATE.VL = srcstep+1
2543 else SVSTATE.VL = srcstep
2546 if SVRMmode.ALL != (el_cond_ok & ctr_ok):
2548 # SVP64 rules about Scalar registers still apply!
2551 # loop finally done, now test if branch (and update LR)
2553 svlr_ok <- SVRMmode.SL
2555 if AA then NIA <-iea EXTS(BD || 0b00)
2556 else NIA <-iea CIA + EXTS(BD || 0b00)
2557 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2558 if SVRMmode.SLu then svlr_ok <- ¬svlr_ok
2559 if lr_ok then LR <-iea CIA + 4
2560 if svlr_ok then SVLR <- SVSTATE
2563 Pseudocode for Vertical-First Mode:
2566 # get SVP64 extended CR field 0..127
2567 SVCRf = SVP64EXTRA(BI>>2)
2569 # select predicate bit or zero/one
2570 if predicate[srcstep]:
2571 if BRc = 1 then # CR0 vectorised
2572 CR{SVCRf+srcstep} = CRbits
2573 testbit = CRbits[BI & 0b11]
2574 else if not SVRMmode.sz:
2575 # inverted CTR test skip mode
2576 if ¬BO[2] & CTRtest & ¬CTI then
2578 SVSTATE.srcstep = new_srcstep
2579 exit # no branch testing
2581 testbit = SVRMmode.SNZ
2582 # actual element test here
2583 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2584 # test for VL to be set (and exit)
2585 if VLSET and cond_ok = VSb then
2587 SVSTATE.VL = new_srcstep+1
2589 SVSTATE.VL = new_srcstep
2592 ### Example Shader code
2595 // assume f() g() or h() modify a and/or b
2605 which compiles to something like:
2610 pred loop_pred = a > 2;
2611 // loop continues while any of a elements greater than 2
2612 while(loop_pred.any()) {
2613 // vector of predicate bits
2614 pred if_pred = loop_pred & (b < 5);
2615 // only call f() if at least 1 bit set
2620 // loop mask ANDs with inverted if-test
2621 pred else_pred = loop_pred & ~if_pred;
2622 // only call g() if at least 1 bit set
2623 if(else_pred.any()) {
2630 which will end up as:
2633 # start from while loop test point
2636 sv.cmpi CR80.v, b.v, 5 # vector compare b into CR64 Vector
2637 sv.bc/m=r30/~ALL/sz CR80.v.LT skip_f # skip when none
2638 # only calculate loop_pred & pred_b because needed in f()
2639 sv.crand CR80.v.SO, CR60.v.GT, CR80.V.LT # if = loop & pred_b
2642 # illustrate inversion of pred_b. invert r30, test ALL
2643 # rather than SOME, but masked-out zero test would FAIL,
2644 # therefore masked-out instead is tested against 1 not 0
2645 sv.bc/m=~r30/ALL/SNZ CR80.v.LT skip_g
2646 # else = loop & ~pred_b, need this because used in g()
2647 sv.crternari(A&~B) CR80.v.SO, CR60.v.GT, CR80.V.LT
2650 # conditionally call h(r30) if any loop pred set
2651 sv.bclr/m=r30/~ALL/sz BO[1]=1 h()
2653 sv.cmpi CR60.v a.v, 2 # vector compare a into CR60 vector
2654 sv.crweird r30, CR60.GT # transfer GT vector to r30
2655 sv.bc/m=r30/~ALL/sz BO[1]=1 while_loop
2661 show why LRu would be useful in a loop. Imagine the following
2665 for (int i = 0; i < 8; i++) {
2670 Under these circumstances exiting from the loop is not only based on
2671 CTR it has become conditional on a CR result. Thus it is desirable that
2672 NIA *and* LR only be modified if the conditions are met
2674 v3.0 pseudocode for `bclrl`:
2677 if (mode_is_64bit) then M <- 0
2679 if ¬BO[2] then CTR <- CTR - 1
2680 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2681 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2682 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
2683 if LK then LR <-iea CIA + 4
2686 the latter part for SVP64 `bclrl` becomes:
2692 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2694 if ctr_ok & cond_ok then
2695 NIA <-iea LR[0:61] || 0b00
2696 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2697 if lr_ok then LR <-iea CIA + 4
2698 # if NIA modified exit loop
2701 The reason why should be clear from this being a Vector loop:
2702 unconditional destruction of LR when LK=1 makes `sv.bclrl` ineffective,
2703 because the intention going into the loop is that the branch should be to
2704 the copy of LR set at the *start* of the loop, not half way through it.
2705 However if the change to LR only occurs if the branch is taken then it
2706 becomes a useful instruction.
2708 The following pseudocode should **not** be implemented because it
2709 violates the fundamental principle of SVP64 which is that SVP64 looping
2710 is a thin wrapper around Scalar Instructions. The pseducode below is
2711 more an actual Vector ISA Branch and as such is not at all appropriate:
2717 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2718 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
2719 # only at the end of looping is LK checked.
2720 # this completely violates the design principle of SVP64
2721 # and would actually need to be a separate (scalar)
2722 # instruction "set LR to CIA+4 but retrospectively"
2723 # which is clearly impossible
2724 if LK then LR <-iea CIA + 4