1 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
3 Credits and acknowledgements:
11 * NLnet Foundation, for funding
12 * OpenPOWER Foundation
15 * IBM for the Power ISA itself
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
23 Simple-V is a type of Vectorisation best described as a "Prefix Loop
24 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the 8086 `REP`
25 Prefix instruction. More advanced features are similar to the Z80
26 `CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces
27 over 1.5 million 64-bit Vector instructions. SVP64, the instruction
28 format, is therefore best viewed as an orthogonal RISC-paradigm "Prefixing"
31 Except where explicitly stated all bit numbers remain as in the rest of
32 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
33 the left and counting up as you move rightwards to the LSB end). All bit
34 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
35 **All register numbering and element numbering however is LSB0 ordering**
36 which is a different convention from that used elsewhere in the Power ISA.
38 The SVP64 prefix always comes before the suffix in PC order and must be
39 considered an independent "Defined word" that augments the behaviour of
40 the following instruction, but does **not** change the actual Decoding
41 of that following instruction. **All prefixed instructions retain their
42 non-prefixed encoding and definition**.
44 Two apparent exceptions to the above hard rule exist: SV Branch-Conditional
45 operations and LD/ST-update "Post-Increment" Mode. Post-Increment
46 was considered sufficiently high priority (significantly reducing hot-loop
47 instruction count) that one bit in the Prefix is reserved for it.
48 Vectorised Branch-Conditional operations "embed" the original Scalar
49 Branch-Conditional behaviour into a much more advanced variant that
50 is highly suited to High-Performance Computation (HPC), Supercomputing,
51 and parallel GPU Workloads.
53 *Architectural Resource Allocation note: it is prohibited to accept RFCs
54 which fundamentally violate this hard requirement. Under no circumstances
55 must the Suffix space have an alternate instruction encoding allocated
56 within SVP64 that is entirely different from the non-prefixed Defined
57 Word. Hardware Implementors critically rely on this inviolate guarantee
58 to implement High-Performance Multi-Issue micro-architectures that can
59 sustain 100% throughput*
61 Subset implementations in hardware are permitted, as long as certain
62 rules are followed, allowing for full soft-emulation including future
63 revisions. Compliancy Subsets exist to ensure minimum levels of binary
64 interoperability expectations within certain environments.
66 ## SVP64 encoding features
68 A number of features need to be compacted into a very small space of
71 * Independent per-register Scalar/Vector tagging and range extension on
73 * Element width overrides on both source and destination
74 * Predication on both source and destination
75 * Two different sources of predication: INT and CR Fields
76 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
77 fail-first and predicate-result mode.
79 Different classes of operations require different formats. The earlier
80 sections cover the common formats and the four separate modes follow:
81 CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
82 and Branch-Conditional.
84 ## Definition of Reserved in this spec.
86 For the new fields added in SVP64, instructions that have any of their
87 fields set to a reserved value must cause an illegal instruction trap,
88 to allow emulation of future instruction sets, or for subsets of SVP64 to
89 be implemented in hardware and the rest emulated. This includes SVP64
90 SPRs: reading or writing values which are not supported in hardware
91 must also raise illegal instruction traps in order to allow emulation.
92 Unless otherwise stated, reserved values are always all zeros.
94 This is unlike OpenPower ISA v3.1, which in many instances does not
95 require a trap if reserved fields are nonzero. Where the standard Power
96 ISA definition is intended the red keyword `RESERVED` is used.
98 ## Definition of "UnVectoriseable"
100 Any operation that inherently makes no sense if repeated is termed
101 "UnVectoriseable" or "UnVectorised". Examples include `sc` or `sync`
102 which have no registers. `mtmsr` is also classed as UnVectoriseable
103 because there is only one `MSR`.
105 ## Register files, elements, and Element-width Overrides
107 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR Register
108 files are expanded from 32 to 128 entries, and the number of CR Fields
109 expanded from CR0-CR7 to CR0-CR127. (Note: A future version of SVP64 is anticipated
110 to extend the VSR register file).
112 Memory access remains exactly the same: the effects of `MSR.LE` remain
113 exactly the same, affecting as they already do and remain **only**
114 on the Load and Store memory-register operation byte-order, and having
115 nothing to do with the ordering of the contents of register files or
116 register-register operations.
118 To be absolutely clear:
121 No conceptual arithmetic ordering or other changes over the Scalar
122 Power ISA definitions to registers or register files or to arithmetic
123 or Logical Operations beyond element-width subdivision and sequential
124 element numbering are expressed or implied
128 numbering is naturally **LSB0-sequentially-incrementing from zero, not
129 MSB0-incrementing** including when element-width overrides are used,
130 at which point the elements progress through each register
131 sequentially from the LSB end
132 (confusingly numbered the highest in MSB0 ordering) and progress
133 incrementally to the MSB end (confusingly numbered the lowest in
136 When exclusively using MSB0-numbering, SVP64
137 becomes unnecessarily complex to both express and subsequently understand:
138 the required conditional subtractions from 63,
139 31, 15 and 7 unfortunately become a hostile minefield, obscuring both
140 intent and meaning. Therefore for the
141 purposes of this section the more natural **LSB0 numbering is assumed**
142 and it is left to the reader to translate to MSB0 numbering.
144 The Canonical specification for how element-sequential numbering and
145 element-width overrides is defined is expressed in the following c
146 structure, assuming a Little-Endian system, and naturally using LSB0
147 numbering everywhere because the ANSI c specification is inherently LSB0:
152 uint8_t b[]; // elwidth 8
153 uint16_t s[]; // elwidth 16
154 uint32_t i[]; // elwidth 32
155 uint64_t l[]; // elwidth 64
156 uint8_t actual_bytes[8];
159 elreg_t int_regfile[128];
161 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
163 case 64: el->l = int_regfile[gpr].l[element];
164 case 32: el->i = int_regfile[gpr].i[element];
165 case 16: el->s = int_regfile[gpr].s[element];
166 case 8 : el->b = int_regfile[gpr].b[element];
169 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
171 case 64: int_regfile[gpr].l[element] = el->l;
172 case 32: int_regfile[gpr].i[element] = el->i;
173 case 16: int_regfile[gpr].s[element] = el->s;
174 case 8 : int_regfile[gpr].b[element] = el->b;
179 Example Vector-looped add operation implementation when elwidths are 64-bit:
182 # add RT, RA,RB using the "uint64_t" union member, "l"
184 int_regfile[RT].l[i] = int_regfile[RA].l[i] + int_regfile[RB].l[i]
187 However if elwidth overrides are set to 16 for both source and destination:
190 # add RT, RA, RB using the "uint64_t" union member "s"
192 int_regfile[RT].s[i] = int_regfile[RA].s[i] + int_regfile[RB].s[i]
195 Hardware Architectural note: to avoid a Read-Modify-Write at the register
196 file it is strongly recommended to implement byte-level write-enable lines
197 exactly as has been implemented in DRAM ICs for many decades. Additionally
198 the predicate mask bit is advised to be associated with the element
199 operation and alongside the result ultimately passed to the register file.
200 When element-width is set to 64-bit the relevant predicate mask bit
201 may be repeated eight times and pull all eight write-port byte-level
202 lines HIGH. Clearly when element-width is set to 8-bit the relevant
203 predicate mask bit corresponds directly with one single byte-level
204 write-enable line. It is up to the Hardware Architect to then amortise
205 (merge) elements together into both PredicatedSIMD Pipelines as well
206 as simultaneous non-overlapping Register File writes, to achieve High
209 ## Scalar Identity Behaviour
211 SVP64 is designed so that when the prefix is all zeros, and
213 influence occurs (no augmentation) such that all standard Power ISA
214 v3.0/v3 1 instructions covered by the prefix are "unaltered". This
215 is termed `scalar identity behaviour` (based on the mathematical
216 definition for "identity", as in, "identity matrix" or better "identity
219 Note that this is completely different from when VL=0. VL=0 turns all
220 operations under its influence into `nops` (regardless of the prefix)
221 whereas when VL=1 and the SV prefix is all zeros, the operation simply
222 acts as if SV had not been applied at all to the instruction (an
223 "identity transformation").
225 The fact that `VL` is dynamic and can be set to any value at runtime based
226 on program conditions and behaviour means very specifically that
227 `scalar identity behaviour` is **not** a redundant encoding. If the
228 only means by which VL could be set was by way of static-compiled
229 immediates then this assertion would be false. VL should not
230 be confused with MAXVL when understanding this key aspect of SimpleV.
232 ## Register Naming and size
234 As indicated above SV Registers are simply the GPR, FPR and CR
235 register files extended linearly to larger sizes; SV Vectorisation
236 iterates sequentially through these registers (LSB0 sequential ordering
239 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
240 r0 to r31, SV extends this as r0 to r127. Likewise FP registers are
241 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
244 The names of the registers therefore reflects a simple linear extension
245 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
246 would be reflected by a linear increase in the size of the underlying
247 SRAM used for the regfiles.
249 Note: when an EXTRA field (defined below) is zero, SV is deliberately
250 designed so that the register fields are identical to as if SV was not in
251 effect i.e. under these circumstances (EXTRA=0) the register field names
252 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
253 This is part of `scalar identity behaviour` described above.
257 With the way that EXTRA fields are defined and applied to register fields,
258 future versions of SV may involve 256 or greater registers. Backwards
259 binary compatibility may be achieved with a PCR bit (Program Compatibility
260 Register). Further discussion is out of scope for this version of SVP64.
262 Additionally, a future variant of SVP64 will be applied to the Scalar
263 (Quad-precision and 128-bit) VSX instructions. Element-width overrides
264 are an opportunity to expand the Power ISA to 256-bit, 512-bit and
271 # New 64-bit Instruction Encoding spaces
273 The following seven new areas are defined within Primary Opcode 9 (EXT009) as a
274 new 64-bit encoding space, alongside EXT1xx.
276 | 0-5 | 6 | 7 | 8-31 | 32| Description |
277 |-----|---|---|-------|---|------------------------------------|
278 | PO | 0 | x | xxxx | 0 | EXT200-231 or `RESERVED2` (56-bit) |
279 | PO | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
280 | PO | 0 | 0 | 0000 | 1 | Scalar EXT232-263 |
281 | PO | 0 | 1 | nnnn | 1 | SVP64:EXT232-263 |
282 | PO | 1 | 0 | 0000 | x | EXT300-363 or `RESERVED1` (32-bit) |
283 | PO | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
284 | PO | 1 | 1 | nnnn | n | SVP64:EXT000-063 |
286 Note that for the future SVP64Single Encoding (currently RESERVED) it
287 is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
289 can be zero (termed `scalar identity behaviour`). This
290 prohibition allows SVP64Single to share its
291 Encoding space with Scalar Ext232-263 and Scalar EXT300-363.
293 *Architectural Resource Allocation Note: **under no circumstances** must
294 different Defined Words be allocated within any `EXT{z}` prefixed
295 or unprefixed space for a given value of `z`. Even if UnVectoriseable
296 an instruction Defined Word space must have the exact same Instruction
297 and exact same Instruction Encoding in all spaces (including
298 being RESERVED if UnVectoriseable) or not be allocated at all.
299 This is required as an inviolate hard rule governing Primary Opcode 9
300 that may not be revoked under any circumstances. A useful way to think
301 of this is that the Prefix Encoding is, like the 8086 REP instruction,
302 an independent 32-bit Defined Word.*
304 Ecoding spaces and their potential are illustrated:
306 | Encoding | Available bits | Scalar | Vectoriseable | SVP64Single |
307 |----------|----------------|--------|---------------|--------------|
308 |EXT000-063| 32 | yes | yes |yes |
309 |EXT100-163| 64 | yes | no |no |
310 |EXT200-231| 56 | N/A |not applicable |not applicable|
311 |EXT232-263| 32 | yes | yes |yes |
312 |EXT300-363| 32 | yes | no |no |
314 Prefixed-Prefixed (96-bit) instructions are prohibited. EXT200-231 presently
315 remains unallocated (RESERVED) and therefore its potential is not yet defined
316 (Not Applicable). Additional Sandbox Opcodes are defined as EXT254 and EXT322,
319 # Remapped Encoding (`RM[0:23]`)
321 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits 32-37 are
322 the Primary Opcode of the Suffix "Defined Word". 38-63 are the remainder of the
323 Defined Word. Note that the new EXT232-263 SVP64 area it is obviously mandatory
324 that bit 32 is required to be set to 1.
326 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
327 |-----|---|---|----------|--------|----------|-----------------------|
328 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
329 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
331 It is important to note that unlike v3.1 64-bit prefixed instructions
332 there is insufficient space in `RM` to provide identification of any SVP64
333 Fields without first partially decoding the 32-bit suffix. Similar to
334 the "Forms" (X-Form, D-Form) the `RM` format is individually associated
335 with every instruction. However this still does not adversely affect Multi-Issue
336 Decoding because the identification of the *length* of anything in the
337 64-bit space has been kept brutally simple (EXT009), and further decoding
338 of any number of 64-bit Encodings in parallel at that point is fully independent.
340 Extreme caution and care must be taken when extending SVP64
341 in future, to not create unnecessary relationships between prefix and
342 suffix that could complicate decoding, adding latency.
346 The following fields are common to all Remapped Encodings:
348 | Field Name | Field bits | Description |
349 |------------|------------|----------------------------------------|
350 | MASKMODE | `0` | Execution (predication) Mask Kind |
351 | MASK | `1:3` | Execution Mask |
352 | SUBVL | `8:9` | Sub-vector length |
354 The following fields are optional or encoded differently depending
355 on context after decoding of the Scalar suffix:
357 | Field Name | Field bits | Description |
358 |------------|------------|----------------------------------------|
359 | ELWIDTH | `4:5` | Element Width |
360 | ELWIDTH_SRC | `6:7` | Element Width for Source |
361 | EXTRA | `10:18` | Register Extra encoding |
362 | MODE | `19:23` | changes Vector behaviour |
364 * MODE changes the behaviour of the SV operation (result saturation,
366 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
367 and Audio/Video DSP work
368 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
370 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
371 sources: scalar INT and Vector CR).
372 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
373 for the instruction, which is determined only by decoding the Scalar 32
376 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
377 such as `RM-1P-3S1D` which indicates for this example that the operation
378 is to be single-predicated and that there are 3 source operand EXTRA
379 tags and one destination operand tag.
381 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
382 or increased latency in some implementations due to lane-crossing.
386 Mode is an augmentation of SV behaviour. Different types of instructions
387 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
388 formats apply to different instruction types. Modes include Reduction,
389 Iteration, arithmetic saturation, and Fail-First. More specific details
390 in each section and in the SVP64 appendix
392 * For condition register operations see [[sv/cr_ops]]
393 * For LD/ST Modes, see [[sv/ldst]].
394 * For Branch modes, see [[sv/branches]]
395 * For arithmetic and logical, see [[sv/normal]]
399 Default behaviour is set to 0b00 so that zeros follow the convention
400 of `scalar identity behaviour`. In this case it means that elwidth
401 overrides are not applicable. Thus if a 32 bit instruction operates
402 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
403 Likewise when a processor is switched from 64 bit to 32 bit mode,
404 `elwidth=0b00` states that, again, the behaviour is not to be modified.
406 Only when elwidth is nonzero is the element width overridden to the
407 explicitly required value.
409 ### Elwidth for Integers:
411 | Value | Mnemonic | Description |
412 |-------|----------------|------------------------------------|
413 | 00 | DEFAULT | default behaviour for operation |
414 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
415 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
416 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
418 This encoding is chosen such that the byte width may be computed as
421 ### Elwidth for FP Registers:
423 | Value | Mnemonic | Description |
424 |-------|----------------|------------------------------------|
425 | 00 | DEFAULT | default behaviour for FP operation |
426 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
427 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
428 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
431 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
432 is reserved for a future implementation of SV
434 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
435 perform its operation at **half** the ELWIDTH then padded back out
436 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
437 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
438 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
439 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
440 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
441 (IEEE754 FP8 or BF8 are not defined).
443 ### Elwidth for CRs (no meaning)
445 Element-width overrides for CR Fields has no meaning. The bits
446 are therefore used for other purposes, or when Rc=1, the Elwidth
447 applies to the result being tested (a GPR or FPR), but not to the
452 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
453 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
454 lines up in combination with all other "default is all zeros" behaviour.
456 | Value | Mnemonic | Subvec | Description |
457 |-------|-----------|---------|------------------------|
458 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
459 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
460 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
461 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
463 The SUBVL encoding value may be thought of as an inclusive range of a
464 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
465 this may be considered to be elements 0b00 to 0b01 inclusive.
467 ## MASK/MASK_SRC & MASKMODE Encoding
469 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
470 types may not be mixed.
472 Special note: to disable predication this field must be set to zero in
473 combination with Integer Predication also being set to 0b000. this has the
474 effect of enabling "all 1s" in the predicate mask, which is equivalent to
475 "not having any predication at all" and consequently, in combination with
476 all other default zeros, fully disables SV (`scalar identity behaviour`).
478 `MASKMODE` may be set to one of 2 values:
480 | Value | Description |
481 |-----------|------------------------------------------------------|
482 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
483 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
485 Integer Twin predication has a second set of 3 bits that uses the same
486 encoding thus allowing either the same register (r3, r10 or r31) to be
487 used for both src and dest, or different regs (one for src, one for dest).
489 Likewise CR based twin predication has a second set of 3 bits, allowing
490 a different test to be applied.
492 Note that it is assumed that Predicate Masks (whether INT or CR) are
493 read *before* the operations proceed. In practice (for CR Fields)
494 this creates an unnecessary block on parallelism. Therefore, it is up
495 to the programmer to ensure that the CR fields used as Predicate Masks
496 are not being written to by any parallel Vector Loop. Doing so results
497 in **UNDEFINED** behaviour, according to the definition outlined in the
498 Power ISA v3.0B Specification.
500 Hardware Implementations are therefore free and clear to delay reading
501 of individual CR fields until the actual predicated element operation
502 needs to take place, safe in the knowledge that no programmer will have
503 issued a Vector Instruction where previous elements could have overwritten
504 (destroyed) not-yet-executed CR-Predicated element operations.
506 ### Integer Predication (MASKMODE=0)
508 When the predicate mode bit is zero the 3 bits are interpreted as below.
509 Twin predication has an identical 3 bit field similarly encoded.
511 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
514 | Value | Mnemonic | Element `i` enabled if: |
515 |-------|----------|------------------------------|
516 | 000 | ALWAYS | predicate effectively all 1s |
517 | 001 | 1 << R3 | `i == R3` |
518 | 010 | R3 | `R3 & (1 << i)` is non-zero |
519 | 011 | ~R3 | `R3 & (1 << i)` is zero |
520 | 100 | R10 | `R10 & (1 << i)` is non-zero |
521 | 101 | ~R10 | `R10 & (1 << i)` is zero |
522 | 110 | R30 | `R30 & (1 << i)` is non-zero |
523 | 111 | ~R30 | `R30 & (1 << i)` is zero |
525 r10 and r30 are at the high end of temporary and unused registers,
526 so as not to interfere with register allocation from ABIs.
528 ### CR-based Predication (MASKMODE=1)
530 When the predicate mode bit is one the 3 bits are interpreted as below.
531 Twin predication has an identical 3 bit field similarly encoded.
533 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
536 | Value | Mnemonic | Element `i` is enabled if |
537 |-------|----------|--------------------------|
538 | 000 | lt | `CR[offs+i].LT` is set |
539 | 001 | nl/ge | `CR[offs+i].LT` is clear |
540 | 010 | gt | `CR[offs+i].GT` is set |
541 | 011 | ng/le | `CR[offs+i].GT` is clear |
542 | 100 | eq | `CR[offs+i].EQ` is set |
543 | 101 | ne | `CR[offs+i].EQ` is clear |
544 | 110 | so/un | `CR[offs+i].FU` is set |
545 | 111 | ns/nu | `CR[offs+i].FU` is clear |
547 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised
548 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
550 The CR Predicates chosen must start on a boundary that Vectorised CR
551 operations can access cleanly, in full. With EXTRA2 restricting starting
552 points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
553 CR Predicate Masks have to be adapted to fit on these boundaries as well.
555 ## Extra Remapped Encoding <a name="extra_remap"> </a>
557 Shows all instruction-specific fields in the Remapped Encoding
558 `RM[10:18]` for all instruction variants. Note that due to the very
559 tight space, the encoding mode is *not* included in the prefix itself.
560 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
561 on a per-instruction basis, and, like "Forms" are given a designation
562 (below) of the form `RM-nP-nSnD`. The full list of which instructions
563 use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV
564 files have been provided which will make the task of creating SV-aware
565 ISA decoders easier*).
567 These mappings are part of the SVP64 Specification in exactly the same
568 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
569 will need a corresponding SVP64 Mapping, which can be derived by-rote
570 from examining the Register "Profile" of the instruction.
572 There are two categories: Single and Twin Predication. Due to space
573 considerations further subdivision of Single Predication is based on
574 whether the number of src operands is 2 or 3. With only 9 bits available
575 some compromises have to be made.
577 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
578 instructions (fmadd, isel, madd).
579 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
580 instructions (src1 src2 dest)
581 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
582 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
583 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
587 | Field Name | Field bits | Description |
588 |------------|------------|----------------------------------------|
589 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
590 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
591 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
592 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
593 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
595 These are for 3 operand in and either 1 or 2 out instructions.
596 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
597 such as `maddedu` have an implicit second destination, RS, the
598 selection of which is determined by bit 18.
602 | Field Name | Field bits | Description |
603 |------------|------------|-------------------------------------------|
604 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
605 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
606 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
608 These are for 2 operand 1 dest instructions, such as `add RT, RA,
609 RB`. However also included are unusual instructions with an implicit
610 dest that is identical to its src reg, such as `rlwinmi`.
612 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
613 not have sufficient bit fields to allow an alternative destination.
614 With SV however this becomes possible. Therefore, the fact that the
615 dest is implicitly also a src should not mislead: due to the *prefix*
616 they are different SV regs.
618 * `rlwimi RA, RS, ...`
619 * Rsrc1_EXTRA3 applies to RS as the first src
620 * Rsrc2_EXTRA3 applies to RA as the secomd src
621 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
623 With the addition of the EXTRA bits, the three registers
624 each may be *independently* made vector or scalar, and be independently
625 augmented to 7 bits in length.
629 | Field Name | Field bits | Description |
630 |------------|------------|----------------------------|
631 | Rdest_EXTRA3 | `10:12` | extends Rdest |
632 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
633 | MASK_SRC | `16:18` | Execution Mask for Source |
635 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
639 single-predicate, three registers (2 read, 1 write)
641 | Field Name | Field bits | Description |
642 |------------|------------|----------------------------|
643 | Rdest_EXTRA3 | `10:12` | extends Rdest |
644 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
645 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
647 ### RM-2P-2S1D/1S2D/3S
649 The primary purpose for this encoding is for Twin Predication on LOAD
650 and STORE operations. see [[sv/ldst]] for detailed anslysis.
654 | Field Name | Field bits | Description |
655 |------------|------------|----------------------------|
656 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
657 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
658 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
659 | MASK_SRC | `16:18` | Execution Mask for Source |
661 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
662 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
664 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src:
665 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
667 Note also that LD with update indexed, which takes 2 src and 2 dest
668 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
669 Twin Predication. therefore these are treated as RM-2P-2S1D and the
670 src spec for RA is also used for the same RA as a dest.
672 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
673 or increased latency in some implementations due to lane-crossing.
677 EXTRA is the means by which two things are achieved:
679 1. Registers are marked as either Vector *or Scalar*
680 2. Register field numbers (limited typically to 5 bit)
681 are extended in range, both for Scalar and Vector.
683 The register files are therefore extended:
685 * INT is extended from r0-31 to r0-127
686 * FP is extended from fp0-32 to fp0-fp127
687 * CR Fields are extended from CR0-7 to CR0-127
689 However due to pressure in `RM.EXTRA` not all these registers
690 are accessible by all instructions, particularly those with
691 a large number of operands (`madd`, `isel`).
693 In the following tables register numbers are constructed from the
694 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
695 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
696 designation for a given instruction. The prefixing is arranged so that
697 interoperability between prefixing and nonprefixing of scalar registers
698 is direct and convenient (when the EXTRA field is all zeros).
700 A pseudocode algorithm explains the relationship, for INT/FP (see
701 SVP64 appendix for CRs)
707 spec = EXTRA2 << 1 # same as EXTRA3, shifted
709 return (RA << 2) | spec[1:2]
711 return (spec[1:2] << 5) | RA
714 Future versions may extend to 256 by shifting Vector numbering up.
715 Scalar will not be altered.
717 Note that in some cases the range of starting points for Vectors
722 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
725 Fields are as follows:
728 * Mode: register is tagged as scalar or vector
729 * Range/Inc: the range of registers accessible from this EXTRA
730 encoding, and the "increment" (accessibility). "/4" means
731 that this EXTRA encoding may only give access (starting point)
733 * MSB..LSB: the bit field showing how the register opcode field
734 combines with EXTRA to give (extend) the register number (GPR)
736 | Value | Mode | Range/Inc | 6..0 |
737 |-----------|-------|---------------|---------------------|
738 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
739 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
740 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
741 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
742 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
743 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
744 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
745 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
749 If EXTRA2 is zero will map to
750 "scalar identity behaviour" i.e Scalar Power ISA register naming:
752 | Value | Mode | Range/inc | 6..0 |
753 |----------|-------|---------------|-----------|
754 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
755 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
756 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
757 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
759 **Note that unlike in EXTRA3, in EXTRA2**:
761 * the GPR Vectors may only start from
762 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
763 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
765 as there is insufficient bits to cover the full range.
769 CR Field encoding is essentially the same but made more complex due to CRs
770 being bit-based, because the application of SVP64 element-numbering applies
771 to the CR *Field* numbering not the CR register *bit* numbering.
772 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
773 and Scalars may only go from `CR0, CR1, ... CR31`
775 Encoding shown MSB down to LSB
777 For a 5-bit operand (BA, BB, BT):
779 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
780 |-------|------|---------------|-----------| --------|---------|
781 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
782 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
783 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
784 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
785 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
786 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
787 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
788 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
790 For a 3-bit operand (e.g. BFA):
792 | Value | Mode | Range/Inc | 6..3 | 2..0 |
793 |-------|------|---------------|-----------| --------|
794 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
795 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
796 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
797 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
798 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
799 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
800 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
801 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
805 CR encoding is essentially the same but made more complex due to CRs
806 being bit-based, because the application of SVP64 element-numbering applies
807 to the CR *Field* numbering not the CR register *bit* numbering.
808 See separate section for explanation and pseudocode.
809 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
811 Encoding shown MSB down to LSB
813 For a 5-bit operand (BA, BB, BC):
815 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
816 |-------|--------|----------------|---------|---------|---------|
817 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
818 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
819 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
820 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
822 For a 3-bit operand (e.g. BFA):
824 | Value | Mode | Range/Inc | 6..3 | 2..0 |
825 |-------|------|---------------|-----------| --------|
826 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
827 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
828 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
829 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
836 # Normal SVP64 Modes, for Arithmetic and Logical Operations
838 Normal SVP64 Mode covers Arithmetic and Logical operations
839 to provide suitable additional behaviour. The Mode
840 field is bits 19-23 of the [[svp64]] RM Field.
844 Mode is an augmentation of SV behaviour, providing additional
845 functionality. Some of these alterations are element-based (saturation),
846 others involve post-analysis (predicate result) and others are
847 Vector-based (mapreduce, fail-on-first).
849 [[sv/ldst]], [[sv/cr_ops]] and [[sv/branches]] are covered separately:
850 the following Modes apply to Arithmetic and Logical SVP64 operations:
852 * **simple** mode is straight vectorisation. no augmentations: the
853 vector comprises an array of independently created results.
854 * **ffirst** or data-dependent fail-on-first: see separate section.
855 the vector may be truncated depending on certain criteria.
856 *VL is altered as a result*.
857 * **sat mode** or saturation: clamps each element result to a min/max
858 rather than overflows / wraps. allows signed and unsigned clamping
860 * **reduce mode**. if used correctly, a mapreduce (or a prefix sum)
861 is performed. see [[svp64/appendix]].
862 note that there are comprehensive caveats when using this mode.
863 * **pred-result** will test the result (CR testing selects a bit of CR
864 and inverts it, just like branch conditional testing) and if the
865 test fails it is as if the *destination* predicate bit was zero even
866 before starting the operation. When Rc=1 the CR element however is
867 still stored in the CR regfile, even if the test failed. See appendix
870 Note that ffirst and reduce modes are not anticipated to be
871 high-performance in some implementations. ffirst due to interactions
872 with VL, and reduce due to it requiring additional operations to produce
873 a result. simple, saturate and pred-result are however inter-element
874 independent and may easily be parallelised to give high performance,
875 regardless of the value of VL.
877 The Mode table for Arithmetic and Logical operations is laid out as
880 | 0-1 | 2 | 3 4 | description |
881 | --- | --- |---------|-------------------------- |
882 | 00 | 0 | dz sz | simple mode |
883 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce) |
884 | 00 | 1 | 1 / | reserved |
885 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
886 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
887 | 10 | N | dz sz | sat mode: N=0/1 u/s |
888 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
889 | 11 | inv | zz RC1 | Rc=0: pred-result z/nonz |
893 * **sz / dz** if predication is enabled will put zeros into the dest
894 (or as src in the case of twin pred) when the predicate bit is zero.
895 otherwise the element is ignored or skipped, depending on context.
896 * **zz**: both sz and dz are set equal to this flag
897 * **inv CR bit** just as in branches (BO) these bits allow testing of
898 a CR bit and whether it is set (inv=0) or unset (inv=1)
899 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
900 than the normal 0..VL-1
901 * **N** sets signed/unsigned saturation.
902 * **RC1** as if Rc=1, enables access to `VLi`.
903 * **VLi** VL inclusive: in fail-first mode, the truncation of
904 VL *includes* the current element at the failure point rather
905 than excludes it from the count.
907 For LD/ST Modes, see [[sv/ldst]]. For Condition Registers see
908 [[sv/cr_ops]]. For Branch modes, see [[sv/branches]].
910 ## Rounding, clamp and saturate
912 To help ensure for example that audio quality is not compromised by
913 overflow, "saturation" is provided, as well as a way to detect when
914 saturation occurred if desired (Rc=1). When Rc=1 there will be a *vector*
915 of CRs, one CR per element in the result (Note: this is different from
916 VSX which has a single CR per block).
918 When N=0 the result is saturated to within the maximum range of an
919 unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
920 logic applies to FP operations, with the result being saturated to
921 maximum rather than returning INF, and the minimum to +0.0
923 When N=1 the same occurs except that the result is saturated to the min
924 or max of a signed result, and for FP to the min and max value rather
925 than returning +/- INF.
927 When Rc=1, the CR "overflow" bit is set on the CR associated with the
928 element, to indicate whether saturation occurred. Note that due to
929 the hugely detrimental effect it has on parallel processing, XER.SO is
930 **ignored** completely and is **not** brought into play here. The CR
931 overflow bit is therefore simply set to zero if saturation did not occur,
932 and to one if it did. This behaviour (ignoring XER.SO) is actually optional in
933 the SFFS Compliancy Subset: for SVP64 it is made mandatory *but only on
934 Vectorised instructions*.
936 Note also that saturate on operations that set OE=1 must raise an Illegal
937 Instruction due to the conflicting use of the CR.so bit for storing if
938 saturation occurred. Vectorised Integer Operations that produce a Carry-Out (CA,
939 CA32): these two bits will be `UNDEFINED` if saturation is also requested.
941 Note that the operation takes place at the maximum bitwidth (max of
942 src and dest elwidth) and that truncation occurs to the range of the
945 *Programmer's Note: Post-analysis of the Vector of CRs to find out if any
946 given element hit saturation may be done using a mapreduced CR op (cror),
947 or by using the new crrweird instruction with Rc=1, which will transfer
948 the required CR bits to a scalar integer and update CR0, which will allow
949 testing the scalar integer for nonzero. see [[sv/cr_int_predication]].
950 Alternatively, a Data-Dependent Fail-First may be used to truncate the
951 Vector Length to non-saturated elements, greatly increasing the productivity
952 of parallelised inner hot-loops.*
956 Reduction in SVP64 is similar in essence to other Vector Processing ISAs,
957 but leverages the underlying scalar Base v3.0B operations. Thus it is
958 more a convention that the programmer may utilise to give the appearance
959 and effect of a Horizontal Vector Reduction. Due to the unusual decoupling
960 it is also possible to perform prefix-sum (Fibonacci Series) in certain
961 circumstances. Details are in the SVP64 appendix
963 Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
964 As explained in the [[sv/appendix]] Reduce Mode switches off the check
965 which would normally stop looping if the result register is scalar.
966 Thus, the result scalar register, if also used as a source scalar,
967 may be used to perform sequential accumulation. This *deliberately*
968 sets up a chain of Register Hazard Dependencies, whereas Parallel Reduce
969 [[sv/remap]] deliberately issues a Tree-Schedule of operations that may
972 ## Data-dependent Fail-on-first
974 Data-dependent fail-on-first is very different from LD/ST Fail-First
975 (also known as Fault-First) and is actually CR-field-driven.
976 Vector elements are required to appear
977 to be executed in sequential Program Order. When REMAP is not active,
978 element 0 would be the first.
980 Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
981 CR-creating operation produces a result (including cmp). Similar to
982 branch, an analysis of the CR is performed and if the test fails, the
983 vector operation terminates and discards all element operations **at and
984 above the current one**, and VL is truncated to either the *previous*
985 element or the current one, depending on whether VLi (VL "inclusive")
986 is clear or set, respectively.
988 Thus the new VL comprises a contiguous vector of results, all of which
989 pass the testing criteria (equal to zero, less than zero etc as defined
992 *Note: when VLi is clear, the behaviour at first seems counter-intuitive.
993 A result is calculated but if the test fails it is prohibited from being
994 actually written. This becomes intuitive again when it is remembered
995 that the length that VL is set to is the number of *written* elements, and
996 only when VLI is set will the current element be included in that count.*
998 The CR-based data-driven fail-on-first is "new" and not found in ARM SVE
999 or RVV. At the same time it is "old" because it is almost identical to
1000 a generalised form of Z80's `CPIR` instruction. It is extremely useful
1001 for reducing instruction count, however requires speculative execution
1002 involving modifications of VL to get high performance implementations.
1003 An additional mode (RC1=1) effectively turns what would otherwise be an
1004 arithmetic operation into a type of `cmp`. The CR is stored (and the
1005 CR.eq bit tested against the `inv` field). If the CR.eq bit is equal to
1006 `inv` then the Vector is truncated and the loop ends.
1008 VLi is only available as an option when `Rc=0` (or for instructions
1009 which do not have Rc). When set, the current element is always also
1010 included in the count (the new length that VL will be set to). This may
1011 be useful in combination with "inv" to truncate the Vector to *exclude*
1012 elements that fail a test, or, in the case of implementations of strncpy,
1013 to include the terminating zero.
1015 In CR-based data-driven fail-on-first there is only the option to select
1016 and test one bit of each CR (just as with branch BO). For more complex
1017 tests this may be insufficient. If that is the case, a vectorised crop
1018 such as crand, cror or [[sv/cr_int_predication]] crweirder may be used,
1019 and ffirst applied to the crop instead of to the arithmetic vector. Note
1020 that crops are covered by the [[sv/cr_ops]] Mode format.
1022 Use of Fail-on-first with Vertical-First Mode is not prohibited but is
1023 not really recommended. The effect of truncating VL
1024 may have unintended and unexpected consequences on subsequent instructions.
1025 VLi set will be fine: it is when VLi is clear that problems may be faced.
1027 *Programmer's note: `VLi` is only accessible in normal operations which in
1028 turn limits the CR field bit-testing to only `EQ/NE`. [[sv/cr_ops]] are
1029 not so limited. Thus it is possible to use for example `sv.cror/ff=gt/vli
1030 *0,*0,*0`, which is not a `nop` because it allows Fail-First Mode to
1031 perform a test and truncate VL.*
1033 *Hardware implementor's note: effective Sequential Program Order must be preserved.
1034 Speculative Execution is perfectly permitted as long as the speculative elements
1035 are held back from writing to register files (kept in Resevation Stations),
1036 until such time as the relevant
1037 CR Field bit(s) has been analysed. All Speculative elements sequentially beyond the
1038 test-failure point **MUST** be cancelled. This is no different from standard
1039 Out-of-Order Execution and the modification effort to efficiently support
1040 Data-Dependent Fail-First within a pre-existing Multi-Issue Out-of-Order Engine
1041 is anticipated to be minimal. In-Order systems on the other hand are expected,
1042 unavoidably, to be low-performance*.
1044 Two extremely important aspects of ffirst are:
1046 * LDST ffirst may never set VL equal to zero. This because on the first
1047 element an exception must be raised "as normal".
1048 * CR-based data-dependent ffirst on the other hand **can** set VL equal
1049 to zero. This is the only means in the entirety of SV that VL may be set
1050 to zero (with the exception of via the SV.STATE SPR). When VL is set
1051 zero due to the first element failing the CR bit-test, all subsequent
1052 vectorised operations are effectively `nops` which is
1053 *precisely the desired and intended behaviour*.
1055 The second crucial aspect, compared to LDST Ffirst:
1057 * LD/ST Failfirst may (beyond the initial first element
1058 conditions) truncate VL for any architecturally suitable reason. Beyond
1059 the first element LD/ST Failfirst is arbitrarily speculative and 100%
1061 * CR-based data-dependent first on the other hand MUST NOT truncate VL
1062 arbitrarily to a length decided by the hardware: VL MUST only be
1063 truncated based explicitly on whether a test fails. This because it is
1064 a precise Deterministic test on which algorithms can and will will rely.
1066 **Floating-point Exceptions**
1068 When Floating-point exceptions are enabled VL must be truncated at
1069 the point where the Exception appears not to have occurred. If `VLi`
1070 is set then VL must include the faulting element, and thus the faulting
1071 element will always raise its exception. If however `VLi` is clear then
1072 VL **excludes** the faulting element and thus the exception will **never**
1075 Although very strongly discouraged the Exception Mode that permits
1076 Floating Point Exception notification to arrive too late to unwind
1077 is permitted (under protest, due it violating the otherwise 100%
1078 Deterministic nature of Data-dependent Fail-first) and is `UNDEFINED`
1081 **Use of lax FP Exception Notification Mode could result in parallel
1082 computations proceeding with invalid results that have to be explicitly
1083 detected, whereas with the strict FP Execption Mode enabled, FFirst
1084 truncates VL, allows subsequent parallel computation to avoid the
1085 exceptions entirely**
1087 ## Data-dependent fail-first on CR operations (crand etc)
1089 Operations that actually produce or alter CR Field as a result have
1090 their own SVP64 Mode, described in [[sv/cr_ops]].
1094 This mode merges common CR testing with predication, saving on instruction
1095 count. Below is the pseudocode excluding predicate zeroing and elwidth
1096 overrides. Note that the pseudocode for SVP64 CR-ops is slightly different.
1100 # predication test, skip all masked out elements.
1101 if predicate_masked_out(i):
1103 result = op(iregs[RA+i], iregs[RB+i])
1104 CRnew = analyse(result) # calculates eq/lt/gt
1105 # Rc=1 always stores the CR field
1107 CR.field[offs+i] = CRnew
1108 # now test CR, similar to branch
1109 if RC1 or CR.field[BO[0:1]] != BO[2]:
1110 continue # test failed: cancel store
1111 # result optionally stored but CR always is
1112 iregs[RT+i] = result
1115 The reason for allowing the CR element to be stored is so that
1116 post-analysis of the CR Vector may be carried out. For example:
1117 Saturation may have occurred (and been prevented from updating, by the
1118 test) but it is desirable to know *which* elements fail saturation.
1120 Note that RC1 Mode basically turns all operations into `cmp`. The
1121 calculation is performed but it is only the CR that is written. The
1122 element result is *always* discarded, never written (just like `cmp`).
1124 Note that predication is still respected: predicate zeroing is slightly
1125 different: elements that fail the CR test *or* are masked out are zero'd.
1135 All Vector ISAs dating back fifty years have extensive and comprehensive
1136 Load and Store operations that go far beyond the capabilities of Scalar
1137 RISC and most CISC processors, yet at their heart on an individual element
1138 basis may be found to be no different from RISC Scalar equivalents.
1140 The resource savings from Vector LD/ST are significant and stem
1141 from the fact that one single instruction can trigger a dozen (or in
1142 some microarchitectures such as Cray or NEC SX Aurora) hundreds of
1143 element-level Memory accesses.
1145 Additionally, and simply: if the Arithmetic side of an ISA supports
1146 Vector Operations, then in order to keep the ALUs 100% occupied the
1147 Memory infrastructure (and the ISA itself) correspondingly needs Vector
1148 Memory Operations as well.
1150 Vectorised Load and Store also presents an extra dimension (literally)
1151 which creates scenarios unique to Vector applications, that a Scalar
1152 (and even a SIMD) ISA simply never encounters. SVP64 endeavours to add
1153 the modes typically found in *all* Scalable Vector ISAs, without changing
1154 the behaviour of the underlying Base (Scalar) v3.0B operations in any way.
1155 (The sole apparent exception is Post-Increment Mode on LD/ST-update instructions)
1159 Vectorisation of Load and Store requires creation, from scalar operations,
1160 a number of different modes:
1162 * **fixed aka "unit" stride** - contiguous sequence with no gaps
1163 * **element strided** - sequential but regularly offset, with gaps
1164 * **vector indexed** - vector of base addresses and vector of offsets
1165 * **Speculative fail-first** - where it makes sense to do so
1166 * **Structure Packing** - covered in SV by [[sv/remap]] and Pack/Unpack Mode.
1168 *Despite being constructed from Scalar LD/ST none of these Modes exist
1169 or make sense in any Scalar ISA. They **only** exist in Vector ISAs*
1171 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
1172 as well as Element-width overrides and Twin-Predication.
1174 Note also that Indexed [[sv/remap]] mode may be applied to both v3.0
1175 LD/ST Immediate instructions *and* v3.0 LD/ST Indexed instructions.
1176 LD/ST-Indexed should not be conflated with Indexed REMAP mode:
1177 clarification is provided below.
1179 **Determining the LD/ST Modes**
1181 A minor complication (caused by the retro-fitting of modern Vector
1182 features to a Scalar ISA) is that certain features do not exactly make
1183 sense or are considered a security risk. Fail-first on Vector Indexed
1184 would allow attackers to probe large numbers of pages from userspace,
1185 where strided fail-first (by creating contiguous sequential LDs) does not.
1187 In addition, reduce mode makes no sense. Realistically we need an
1188 alternative table definition for [[sv/svp64]] `RM.MODE`. The following
1192 * predicate-result (mostly for cache-inhibited LD/ST)
1193 * simple (no augmentation)
1194 * fail-first (where Vector Indexed is banned)
1195 * Signed Effective Address computation (Vector Indexed only)
1197 More than that however it is necessary to fit the usual Vector ISA
1198 capabilities onto both Power ISA LD/ST with immediate and to LD/ST
1199 Indexed. They present subtly different Mode tables, which, due to lack
1200 of space, have the following quirks:
1202 * LD/ST Immediate has no individual control over src/dest zeroing,
1203 whereas LD/ST Indexed does.
1204 * LD/ST Indexed has no Pack/Unpack (REMAP may be used instead)
1206 ## Format and fields
1208 Fields used in tables below:
1210 * **sz / dz** if predication is enabled will put zeros into the dest
1211 (or as src in the case of twin pred) when the predicate bit is zero.
1212 otherwise the element is ignored or skipped, depending on context.
1213 * **zz**: both sz and dz are set equal to this flag.
1214 * **inv CR bit** just as in branches (BO) these bits allow testing of
1215 a CR bit and whether it is set (inv=0) or unset (inv=1)
1216 * **N** sets signed/unsigned saturation.
1217 * **RC1** as if Rc=1, stores CRs *but not the result*
1218 * **SEA** - Signed Effective Address, if enabled performs sign-extension on
1219 registers that have been reduced due to elwidth overrides
1220 * **PI** - post-increment mode (applies to LD/ST with update only).
1221 the Effective Address utilised is always just RA, i.e. the computation of
1222 EA is stored in RA **after** it is actually used.
1223 * **LF** - Load/Store Fail or Fault First: for any reason Load or Store Vectors
1224 may be truncated to (at least) one element, and VL altered to indicate such.
1228 The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE`
1229 (bits 19:23 of `RM`) is:
1231 | 0-1 | 2 | 3 4 | description |
1232 | --- | --- |---------|--------------------------- |
1233 | 00 | 0 | zz els | simple mode |
1234 | 00 | 1 | PI LF | post-increment and Fault-First |
1235 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1236 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1237 | 10 | N | zz els | sat mode: N=0/1 u/s |
1238 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1239 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1241 The `els` bit is only relevant when `RA.isvec` is clear: this indicates
1242 whether stride is unit or element:
1246 svctx.ldstmode = indexed
1248 svctx.ldstmode = unitstride
1249 elif immediate != 0:
1250 svctx.ldstmode = elementstride
1253 An immediate of zero is a safety-valve to allow `LD-VSPLAT`: in effect
1254 the multiplication of the immediate-offset by zero results in reading from
1255 the exact same memory location, *even with a Vector register*. (Normally
1256 this type of behaviour is reserved for the mapreduce modes)
1258 For `LD-VSPLAT`, on non-cache-inhibited Loads, the read can occur just
1259 the once and be copied, rather than hitting the Data Cache multiple
1260 times with the same memory read at the same location. The benefit of
1261 Cache-inhibited LD-splats is that it allows for memory-mapped peripherals
1262 to have multiple data values read in quick succession and stored in
1263 sequentially numbered registers (but, see Note below).
1265 For non-cache-inhibited ST from a vector source onto a scalar destination:
1266 with the Vector loop effectively creating multiple memory writes to
1267 the same location, we can deduce that the last of these will be the
1268 "successful" one. Thus, implementations are free and clear to optimise
1269 out the overwriting STs, leaving just the last one as the "winner".
1270 Bear in mind that predicate masks will skip some elements (in source
1271 non-zeroing mode). Cache-inhibited ST operations on the other hand
1272 **MUST** write out a Vector source multiple successive times to the exact
1273 same Scalar destination. Just like Cache-inhibited LDs, multiple values
1274 may be written out in quick succession to a memory-mapped peripheral
1275 from sequentially-numbered registers.
1277 Note that any memory location may be Cache-inhibited
1278 (Power ISA v3.1, Book III, 1.6.1, p1033)
1280 *Programmer's Note: an immediate also with a Scalar source as a "VSPLAT"
1281 mode is simply not possible: there are not enough Mode bits. One single
1282 Scalar Load operation may be used instead, followed by any arithmetic
1283 operation (including a simple mv) in "Splat" mode.*
1287 The modes for `RA+RB` indexed version are slightly different
1288 but are the same `RM.MODE` bits (19:23 of `RM`):
1290 | 0-1 | 2 | 3 4 | description |
1291 | --- | --- |---------|-------------------------- |
1292 | 00 | SEA | dz sz | simple mode |
1293 | 01 | SEA | dz sz | Strided (scalar only source) |
1294 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1295 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1296 | 11 | inv | zz RC1 | Rc=0: pred-result z/nonz |
1298 Vector Indexed Strided Mode is qualified as follows:
1300 if mode = 0b01 and !RA.isvec and !RB.isvec:
1301 svctx.ldstmode = elementstride
1303 A summary of the effect of Vectorisation of src or dest:
1306 imm(RA) RT.v RA.v no stride allowed
1307 imm(RA) RT.s RA.v no stride allowed
1308 imm(RA) RT.v RA.s stride-select allowed
1309 imm(RA) RT.s RA.s not vectorised
1310 RA,RB RT.v {RA|RB}.v Standard Indexed
1311 RA,RB RT.s {RA|RB}.v Indexed but single LD (no VSPLAT)
1312 RA,RB RT.v {RA&RB}.s VSPLAT possible. stride selectable
1313 RA,RB RT.s {RA&RB}.s not vectorised (scalar identity)
1316 Signed Effective Address computation is only relevant for Vector Indexed
1317 Mode, when elwidth overrides are applied. The source override applies to
1318 RB, and before adding to RA in order to calculate the Effective Address,
1319 if SEA is set RB is sign-extended from elwidth bits to the full 64 bits.
1320 For other Modes (ffirst, saturate), all EA computation with elwidth
1321 overrides is unsigned.
1323 Note that cache-inhibited LD/ST when VSPLAT is activated will perform
1324 **multiple** LD/ST operations, sequentially. Even with scalar src
1325 a Cache-inhibited LD will read the same memory location *multiple
1326 times*, storing the result in successive Vector destination registers.
1327 This because the cache-inhibit instructions are typically used to read
1328 and write memory-mapped peripherals. If a genuine cache-inhibited
1329 LD-VSPLAT is required then a single *scalar* cache-inhibited LD should
1330 be performed, followed by a VSPLAT-augmented mv, copying the one *scalar*
1331 value into multiple register destinations.
1333 Note also that cache-inhibited VSPLAT with Predicate-result is possible.
1334 This allows for example to issue a massive batch of memory-mapped
1335 peripheral reads, stopping at the first NULL-terminated character and
1336 truncating VL to that point. No branch is needed to issue that large
1337 burst of LDs, which may be valuable in Embedded scenarios.
1339 ## Vectorisation of Scalar Power ISA v3.0B
1341 Scalar Power ISA Load/Store operations may be seen from their
1342 pseudocode to be of the form:
1350 and for immediate variants:
1358 Thus in the first example, the source registers may each be independently
1359 marked as scalar or vector, and likewise the destination; in the second
1360 example only the one source and one dest may be marked as scalar or
1363 Thus we can see that Vector Indexed may be covered, and, as demonstrated
1364 with the pseudocode below, the immediate can be used to give unit
1365 stride or element stride. With there being no way to tell which from
1366 the Power v3.0B Scalar opcode alone, the choice is provided instead by
1370 # LD not VLD! format - ldop RT, immed(RA)
1371 # op_width: lb=1, lh=2, lw=4, ld=8
1372 op_load(RT, RA, op_width, immed, svctx, RAupdate):
1373 ps = get_pred_val(FALSE, RA); # predication on src
1374 pd = get_pred_val(FALSE, RT); # ... AND on dest
1375 for (i=0, j=0, u=0; i < VL && j < VL;):
1376 # skip nonpredicates elements
1377 if (RA.isvec) while (!(ps & 1<<i)) i++;
1378 if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
1379 if (RT.isvec) while (!(pd & 1<<j)) j++;
1381 offs = 0; # added afterwards
1382 if RA.isvec: srcbase = ireg[RA+i]
1383 else srcbase = ireg[RA]
1384 elif svctx.ldstmode == elementstride:
1385 # element stride mode
1387 offs = i * immed # j*immed for a ST
1388 elif svctx.ldstmode == unitstride:
1391 offs = immed + (i * op_width) # j*op_width for ST
1393 # quirky Vector indexed mode but with an immediate
1394 srcbase = ireg[RA+i]
1397 # standard scalar mode (but predicated)
1398 # no stride multiplier means VSPLAT mode
1405 ireg[RT+j] <= MEM[EA];
1406 # check post-increment of EA
1407 if postinc: EA = srcbase + immed;
1409 if RAupdate: ireg[RAupdate+u] = EA;
1411 break # destination scalar, end now
1413 if (RAupdate.isvec) u++;
1420 # format: ldop RT, RA, RB
1421 function op_ldx(RT, RA, RB, RAupdate=False) # LD not VLD!
1422 ps = get_pred_val(FALSE, RA); # predication on src
1423 pd = get_pred_val(FALSE, RT); # ... AND on dest
1424 for (i=0, j=0, k=0, u=0; i < VL && j < VL && k < VL):
1425 # skip nonpredicated RA, RB and RT
1426 if (RA.isvec) while (!(ps & 1<<i)) i++;
1427 if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
1428 if (RB.isvec) while (!(ps & 1<<k)) k++;
1429 if (RT.isvec) while (!(pd & 1<<j)) j++;
1430 if svctx.ldstmode == elementstride:
1431 EA = ireg[RA] + ireg[RB]*j # register-strided
1433 EA = ireg[RA+i] + ireg[RB+k] # indexed address
1434 if RAupdate: ireg[RAupdate+u] = EA
1435 ireg[RT+j] <= MEM[EA];
1437 break # destination scalar, end immediately
1439 if (RAupdate.isvec) u++;
1444 Note that Element-Strided uses the Destination Step because with both
1445 sources being Scalar as a prerequisite condition of activation of
1446 Element-Stride Mode, the source step (being Scalar) would never advance.
1448 Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update"
1449 mode (`ldux`) to be effectively a *completely different* register from
1450 RA-as-a-source. This because there is room in svp64 to extend RA-as-src
1451 as well as RA-as-dest, both independently as scalar or vector *and*
1452 independently extending their range.
1454 *Programmer's note: being able to set RA-as-a-source as separate from
1455 RA-as-a-destination as Scalar is **extremely valuable** once it is
1456 remembered that Simple-V element operations must be in Program Order,
1457 especially in loops, for saving on multiple address computations. Care
1458 does have to be taken however that RA-as-src is not overwritten by
1459 RA-as-dest unless intentionally desired, especially in element-strided
1462 ## LD/ST Indexed vs Indexed REMAP
1464 Unfortunately the word "Indexed" is used twice in completely different
1465 contexts, potentially causing confusion.
1467 * There has existed instructions in the Power ISA `ld RT,RA,RB` since
1468 its creation: these are called "LD/ST Indexed" instructions and their
1469 name and meaning is well-established.
1470 * There now exists, in Simple-V, a REMAP mode called "Indexed"
1471 Mode that can be applied to *any* instruction **including those
1472 named LD/ST Indexed**.
1474 Whilst it may be costly in terms of register reads to allow REMAP Indexed
1475 Mode to be applied to any Vectorised LD/ST Indexed operation such as
1476 `sv.ld *RT,RA,*RB`, or even misleadingly labelled as redundant, firstly
1477 the strict application of the RISC Paradigm that Simple-V follows makes
1478 it awkward to consider *preventing* the application of Indexed REMAP to
1479 such operations, and secondly they are not actually the same at all.
1481 Indexed REMAP, as applied to RB in the instruction `sv.ld *RT,RA,*RB`
1482 effectively performs an *in-place* re-ordering of the offsets, RB.
1483 To achieve the same effect without Indexed REMAP would require taking
1484 a *copy* of the Vector of offsets starting at RB, manually explicitly
1485 reordering them, and finally using the copy of re-ordered offsets in a
1486 non-REMAP'ed `sv.ld`. Using non-strided LD as an example, pseudocode
1487 showing what actually occurs, where the pseudocode for `indexed_remap`
1488 may be found in [[sv/remap]]:
1491 # sv.ld *RT,RA,*RB with Index REMAP applied to RB
1494 rb_idx = indexed_remap(i) # remap
1496 rb_idx = i # use the index as-is
1497 EA = GPR(RA) + GPR(RB+rb_idx)
1498 GPR(RT+i) = MEM(EA, 8)
1501 Thus it can be seen that the use of Indexed REMAP saves copying
1502 and manual reordering of the Vector of RB offsets.
1506 LD/ST ffirst treats the first LD/ST in a vector (element 0 if REMAP
1507 is not active) as an ordinary one, with all behaviour with respect to
1508 Interrupts Exceptions Page Faults Memory Management being identical
1509 in every regard to Scalar v3.0 Power ISA LD/ST. However for elements
1510 1 and above, if an exception would occur, then VL is **truncated**
1511 to the previous element: the exception is **not** then raised because
1512 the LD/ST that would otherwise have caused an exception is *required*
1513 to be cancelled. Additionally an implementor may choose to truncate VL
1514 for any arbitrary reason *except for the very first*.
1516 ffirst LD/ST to multiple pages via a Vectorised Index base is
1517 considered a security risk due to the abuse of probing multiple
1518 pages in rapid succession and getting speculative feedback on which
1519 pages would fail. Therefore Vector Indexed LD/ST is prohibited
1520 entirely, and the Mode bit instead used for element-strided LD/ST.
1523 for(i = 0; i < VL; i++)
1524 reg[rt + i] = mem[reg[ra] + i * reg[rb]];
1527 High security implementations where any kind of speculative probing of
1528 memory pages is considered a risk should take advantage of the fact
1529 that implementations may truncate VL at any point, without requiring
1530 software to be rewritten and made non-portable. Such implementations may
1531 choose to *always* set VL=1 which will have the effect of terminating
1532 any speculative probing (and also adversely affect performance), but
1533 will at least not require applications to be rewritten.
1535 Low-performance simpler hardware implementations may also choose (always)
1536 to also set VL=1 as the bare minimum compliant implementation of LD/ST
1537 Fail-First. It is however critically important to remember that the first
1538 element LD/ST **MUST** be treated as an ordinary LD/ST, i.e. **MUST**
1539 raise exceptions exactly like an ordinary LD/ST.
1541 For ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value
1542 for any implementation-specific reason. For example: it is perfectly
1543 reasonable for implementations to alter VL when ffirst LD or ST operations
1544 are initiated on a nonaligned boundary, such that within a loop the
1545 subsequent iteration of that loop begins the following ffirst LD/ST
1546 operations on an aligned boundary such as the beginning of a cache line,
1547 or beginning of a Virtual Memory page. Likewise, to reduce workloads or
1550 Vertical-First Mode is slightly strange in that only one element at a time
1551 is ever executed anyway. Given that programmers may legitimately choose
1552 to alter srcstep and dststep in non-sequential order as part of explicit
1553 loops, it is neither possible nor safe to make speculative assumptions
1554 about future LD/STs. Therefore, Fail-First LD/ST in Vertical-First is
1555 `UNDEFINED`. This is very different from Arithmetic (Data-dependent)
1556 FFirst where Vertical-First Mode is fully deterministic, not speculative.
1558 ## LOAD/STORE Elwidths <a name="elwidth"></a>
1560 Loads and Stores are almost unique in that the Power Scalar ISA
1561 provides a width for the operation (lb, lh, lw, ld). Only `extsb` and
1562 others like it provide an explicit operation width. There are therefore
1563 *three* widths involved:
1565 * operation width (lb=8, lh=16, lw=32, ld=64)
1566 * src element width override (8/16/32/default)
1567 * destination element width override (8/16/32/default)
1569 Some care is therefore needed to express and make clear the transformations,
1570 which are expressly in this order:
1572 * Calculate the Effective Address from RA at full width
1573 but (on Indexed Load) allow srcwidth overrides on RB
1574 * Load at the operation width (lb/lh/lw/ld) as usual
1575 * byte-reversal as usual
1576 * Non-saturated mode:
1577 - zero-extension or truncation from operation width to dest elwidth
1578 - place result in destination at dest elwidth
1580 - Sign-extension or truncation from operation width to dest width
1581 - signed/unsigned saturation down to dest elwidth
1583 In order to respect Power v3.0B Scalar behaviour the memory side
1584 is treated effectively as completely separate and distinct from SV
1585 augmentation. This is primarily down to quirks surrounding LE/BE and
1588 It is rather unfortunately possible to request an elwidth override on
1589 the memory side which does not mesh with the overridden operation width:
1590 these result in `UNDEFINED` behaviour. The reason is that the effect
1591 of attempting a 64-bit `sv.ld` operation with a source elwidth override
1592 of 8/16/32 would result in overlapping memory requests, particularly
1593 on unit and element strided operations. Thus it is `UNDEFINED` when
1594 the elwidth is smaller than the memory operation width. Examples include
1595 `sv.lw/sw=16/els` which requests (overlapping) 4-byte memory reads offset
1596 from each other at 2-byte intervals. Store likewise is also `UNDEFINED`
1597 where the dest elwidth override is less than the operation width.
1599 Note the following regarding the pseudocode to follow:
1601 * `scalar identity behaviour` SV Context parameter conditions turn this
1602 into a straight absolute fully-compliant Scalar v3.0B LD operation
1603 * `brev` selects whether the operation is the byte-reversed variant (`ldbrx`
1605 * `op_width` specifies the operation width (`lb`, `lh`, `lw`, `ld`) as
1606 a "normal" part of Scalar v3.0B LD
1607 * `imm_offs` specifies the immediate offset `ld r3, imm_offs(r5)`, again
1608 as a "normal" part of Scalar v3.0B LD
1609 * `svctx` specifies the SV Context and includes VL as well as
1610 source and destination elwidth overrides.
1612 Below is the pseudocode for Unit-Strided LD (which includes Vector
1613 capability). Observe in particular that RA, as the base address in both
1614 Immediate and Indexed LD/ST, does not have element-width overriding
1617 Note that predication, predication-zeroing, and other modes except
1618 saturation have all been removed, for clarity and simplicity:
1622 # this covers unit stride mode and a type of vector offset
1623 function op_ld(RT, RA, op_width, imm_offs, svctx)
1624 for (int i = 0, int j = 0; i < svctx.VL && j < svctx.VL):
1625 if not svctx.unit/el-strided:
1626 # strange vector mode, compute 64 bit address which is
1627 # not polymorphic! elwidth hardcoded to 64 here
1628 srcbase = get_polymorphed_reg(RA, 64, i)
1630 # unit / element stride mode, compute 64 bit address
1631 srcbase = get_polymorphed_reg(RA, 64, 0)
1632 # adjust for unit/el-stride
1635 # read the underlying memory
1636 memread <= MEM(srcbase + imm_offs, op_width)
1639 if svpctx.saturation_mode:
1640 # ... saturation adjustment...
1641 memread = clamp(memread, op_width, svctx.dest_elwidth)
1643 # truncate/extend to over-ridden dest width.
1644 memread = adjust_wid(memread, op_width, svctx.dest_elwidth)
1646 # takes care of inserting memory-read (now correctly byteswapped)
1647 # into regfile underlying LE-defined order, into the right place
1648 # within the NEON-like register, respecting destination element
1649 # bitwidth, and the element index (j)
1650 set_polymorphed_reg(RT, svctx.dest_elwidth, j, memread)
1652 # increments both src and dest element indices (no predication here)
1657 Note above that the source elwidth is *not used at all* in LD-immediate.
1659 For LD/Indexed, the key is that in the calculation of the Effective Address,
1660 RA has no elwidth override but RB does. Pseudocode below is simplified
1661 for clarity: predication and all modes except saturation are removed:
1664 # LD not VLD! ld*rx if brev else ld*
1665 function op_ld(RT, RA, RB, op_width, svctx, brev)
1666 for (int i = 0, int j = 0; i < svctx.VL && j < svctx.VL):
1667 if not svctx.el-strided:
1668 # RA not polymorphic! elwidth hardcoded to 64 here
1669 srcbase = get_polymorphed_reg(RA, 64, i)
1671 # element stride mode, again RA not polymorphic
1672 srcbase = get_polymorphed_reg(RA, 64, 0)
1673 # RB *is* polymorphic
1674 offs = get_polymorphed_reg(RB, svctx.src_elwidth, i)
1676 if svctx.SEA: offs = sext(offs, svctx.src_elwidth, 64)
1678 # takes care of (merges) processor LE/BE and ld/ldbrx
1679 bytereverse = brev XNOR MSR.LE
1681 # read the underlying memory
1682 memread <= MEM(srcbase + offs, op_width)
1684 # optionally performs byteswap at op width
1686 memread = byteswap(memread, op_width)
1688 if svpctx.saturation_mode:
1689 # ... saturation adjustment...
1690 memread = clamp(memread, op_width, svctx.dest_elwidth)
1692 # truncate/extend to over-ridden dest width.
1693 memread = adjust_wid(memread, op_width, svctx.dest_elwidth)
1695 # takes care of inserting memory-read (now correctly byteswapped)
1696 # into regfile underlying LE-defined order, into the right place
1697 # within the NEON-like register, respecting destination element
1698 # bitwidth, and the element index (j)
1699 set_polymorphed_reg(RT, svctx.dest_elwidth, j, memread)
1701 # increments both src and dest element indices (no predication here)
1708 In the [[sv/remap]] page the concept of "Remapping" is described. Whilst
1709 it is expensive to set up (2 64-bit opcodes minimum) it provides a way to
1710 arbitrarily perform 1D, 2D and 3D "remapping" of up to 64 elements worth
1711 of LDs or STs. The usual interest in such re-mapping is for example in
1712 separating out 24-bit RGB channel data into separate contiguous registers.
1714 REMAP easily covers this capability, and with dest elwidth overrides
1715 and saturation may do so with built-in conversion that would normally
1716 require additional width-extension, sign-extension and min/max Vectorised
1717 instructions as post-processing stages.
1719 Thus we do not need to provide specialist LD/ST "Structure Packed" opcodes
1720 because the generic abstracted concept of "Remapping", when applied to
1721 LD/ST, will give that same capability, with far more flexibility.
1723 It is worth noting that Pack/Unpack Modes of SVSTATE, which may be
1724 established through `svstep`, are also an easy way to perform regular
1725 Structure Packing, at the vec2/vec3/vec4 granularity level. Beyond that,
1726 REMAP will need to be used.
1732 # Condition Register SVP64 Operations
1734 Condition Register Fields are only 4 bits wide: this presents some
1735 interesting conceptual challenges for SVP64, which was designed
1736 primarily for vectors of arithmetic and logical operations. However
1737 if predicates may be bits of CR Fields it makes sense to extend
1738 Simple-V to cover CR Operations, especially given that Vectorised Rc=1
1739 may be processed by Vectorised CR Operations tbat usefully in turn
1740 may become Predicate Masks to yet more Vector operations, like so:
1743 sv.cmpi/ew=8 *B,*ra,0 # compare bytes against zero
1744 sv.cmpi/ew=8 *B2,*ra,13. # and against newline
1745 sv.cror PM.EQ,B.EQ,B2.EQ # OR compares to create mask
1746 sv.stb/sm=EQ ... # store only nonzero/newline
1749 Element width however is clearly meaningless for a 4-bit collation of
1750 Conditions, EQ LT GE SO. Likewise, arithmetic saturation (an important
1751 part of Arithmetic SVP64) has no meaning. An alternative Mode Format is
1752 required, and given that elwidths are meaningless for CR Fields the bits
1753 in SVP64 `RM` may be used for other purposes.
1755 This alternative mapping **only** applies to instructions that **only**
1756 reference a CR Field or CR bit as the sole exclusive result. This section
1757 **does not** apply to instructions which primarily produce arithmetic
1758 results that also, as an aside, produce a corresponding CR Field (such as
1759 when Rc=1). Instructions that involve Rc=1 are definitively arithmetic
1760 in nature, where the corresponding Condition Register Field can be
1761 considered to be a "co-result". Such CR Field "co-result" arithmeric
1762 operations are firmly out of scope for this section, being covered fully
1765 * Examples of v3.0B instructions to which this section does
1767 - `mfcr` and `cmpi` (3 bit operands) and
1768 - `crnor` and `crand` (5 bit operands).
1769 * Examples to which this section does **not** apply include
1770 `fadds.` and `subf.` which both produce arithmetic results
1771 (and a CR Field co-result).
1773 The CR Mode Format still applies to `sv.cmpi` because despite
1774 taking a GPR as input, the output from the Base Scalar v3.0B `cmpi`
1775 instruction is purely to a Condition Register Field.
1777 Other modes are still applicable and include:
1779 * **Data-dependent fail-first**.
1780 useful to truncate VL based on analysis of a Condition Register result bit.
1782 Reduction is useful for analysing a Vector of Condition Register Fields
1783 and reducing it to one single Condition Register Field.
1785 Predicate-result does not make any sense because when Rc=1 a co-result
1786 is created (a CR Field). Testing the co-result allows the decision to
1787 be made to store or not store the main result, and for CR Ops the CR
1788 Field result *is* the main result.
1792 SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
1794 |6 | 7 |19-20| 21 | 22 23 | description |
1795 |--|---|-----| --- |---------|----------------- |
1796 |/ | / |0 RG | 0 | dz sz | simple mode |
1797 |/ | / |0 RG | 1 | dz sz | scalar reduce mode (mapreduce) |
1798 |zz|SNZ|1 VLI| inv | CR-bit | Ffirst 3-bit mode |
1799 |/ |SNZ|1 VLI| inv | dz sz | Ffirst 5-bit mode (implies CR-bit from result) |
1803 * **sz / dz** if predication is enabled will put zeros into the dest
1804 (or as src in the case of twin pred) when the predicate bit is zero.
1805 otherwise the element is ignored or skipped, depending on context.
1806 * **zz** set both sz and dz equal to this flag
1807 * **SNZ** In fail-first mode, on the bit being tested, when sz=1 and
1808 SNZ=1 a value "1" is put in place of "0".
1809 * **inv CR-bit** just as in branches (BO) these bits allow testing of
1810 a CR bit and whether it is set (inv=0) or unset (inv=1)
1811 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
1812 than the normal 0..VL-1
1813 * **SVM** sets "subvector" reduce mode
1814 * **VLi** VL inclusive: in fail-first mode, the truncation of
1815 VL *includes* the current element at the failure point rather
1816 than excludes it from the count.
1818 ## Data-dependent fail-first on CR operations
1820 The principle of data-dependent fail-first is that if, during the course
1821 of sequentially evaluating an element's Condition Test, one such test
1822 is encountered which fails, then VL (Vector Length) is truncated (set)
1823 at that point. In the case of Arithmetic SVP64 Operations the Condition
1824 Register Field generated from Rc=1 is used as the basis for the truncation
1825 decision. However with CR-based operations that CR Field result to be
1826 tested is provided *by the operation itself*.
1828 Data-dependent SVP64 Vectorised Operations involving the creation
1829 or modification of a CR can require an extra two bits, which are not
1830 available in the compact space of the SVP64 RM `MODE` Field. With the
1831 concept of element width overrides being meaningless for CR Fields it
1832 is possible to use the `ELWIDTH` field for alternative purposes.
1834 Condition Register based operations such as `sv.mfcr` and `sv.crand`
1835 can thus be made more flexible. However the rules that apply in this
1836 section also apply to future CR-based instructions.
1838 There are two primary different types of CR operations:
1840 * Those which have a 3-bit operand field (referring to a CR Field)
1841 * Those which have a 5-bit operand (referring to a bit within the
1844 Examining these two types it is observed that the difference may
1845 be considered to be that the 5-bit variant *already* provides the
1846 prerequisite information about which CR Field bit (EQ, GE, LT, SO) is
1847 to be operated on by the instruction. Thus, logically, we may set the
1850 * When a 5-bit CR Result field is used in an instruction, the
1851 5-bit variant of Data-Dependent Fail-First
1852 must be used. i.e. the bit of the CR field to be tested is
1853 the one that has just been modified (created) by the operation.
1854 * When a 3-bit CR Result field is used the 3-bit variant
1855 must be used, providing as it does the missing `CRbit` field
1856 in order to select which CR Field bit of the result shall
1857 be tested (EQ, LE, GE, SO)
1859 The reason why the 3-bit CR variant needs the additional CR-bit field
1860 should be obvious from the fact that the 3-bit CR Field from the base
1861 Power ISA v3.0B operation clearly does not contain and is missing the
1862 two CR Field Selector bits. Thus, these two bits (to select EQ, LE,
1863 GE or SO) must be provided in another way.
1865 Examples of the former type:
1867 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
1868 to be tested against `inv` is the one selected by `BT`
1869 * mcrf. This has only 3-bit (BF, BFA). In order to select the
1870 bit to be tested, the alternative encoding must be used.
1871 With `CRbit` coming from the SVP64 RM bits 22-23 the bit
1872 of BF to be tested is identified.
1874 Just as with SVP64 [[sv/branches]] there is the option to truncate
1875 VL to include the element being tested (`VLi=1`) and to exclude it
1878 Also exactly as with [[sv/normal]] fail-first, VL cannot, unlike
1879 [[sv/ldst]], be set to an arbitrary value. Deterministic behaviour
1882 ## Reduction and Iteration
1884 Bearing in mind as described in the svp64 Appendix, SVP64 Horizontal
1885 Reduction is a deterministic schedule on top of base Scalar v3.0
1886 operations, the same rules apply to CR Operations, i.e. that programmers
1887 must follow certain conventions in order for an *end result* of a
1888 reduction to be achieved. Unlike other Vector ISAs *there are no explicit
1889 reduction opcodes* in SVP64: Schedules however achieve the same effect.
1891 Due to these conventions only reduction on operations such as `crand`
1892 and `cror` are meaningful because these have Condition Register Fields
1893 as both input and output. Meaningless operations are not prohibited
1894 because the cost in hardware of doing so is prohibitive, but neither
1895 are they `UNDEFINED`. Implementations are still required to execute them
1896 but are at liberty to optimise out any operations that would ultimately
1897 be overwritten, as long as Strict Program Order is still obvservable by
1900 Also bear in mind that 'Reverse Gear' may be enabled, which can be
1901 used in combination with overlapping CR operations to iteratively
1902 accumulate results. Issuing a `sv.crand` operation for example with
1903 `BA` differing from `BB` by one Condition Register Field would result
1904 in a cascade effect, where the first-encountered CR Field would set the
1905 result to zero, and also all subsequent CR Field elements thereafter:
1908 # sv.crand/mr/rg CR4.ge.v, CR5.ge.v, CR4.ge.v
1909 for i in VL-1 downto 0 # reverse gear
1910 CR.field[4+i].ge &= CR.field[5+i].ge
1913 `sv.crxor` with reduction would be particularly useful for parity
1914 calculation for example, although there are many ways in which the same
1915 calculation could be carried out after transferring a vector of CR Fields
1916 to a GPR using crweird operations.
1918 Implementations are free and clear to optimise these reductions in any way
1919 they see fit, as long as the end-result is compatible with Strict Program
1920 Order being observed, and Interrupt latency is not adversely impacted.
1922 ## Unusual and quirky CR operations
1924 **cmp and other compare ops**
1926 `cmp` and `cmpi` etc take GPRs as sources and create a CR Field as a result.
1931 With `ELWIDTH` applying to the source GPR operands this is perfectly fine.
1933 **crweird operations**
1935 There are 4 weird CR-GPR operations and one reasonable one in
1936 the [[cr_int_predication]] set:
1942 * mcrfm - reasonably normal and referring to CR Fields for src and dest.
1944 The "weird" operations have a non-standard behaviour, being able to
1945 treat *individual bits* of a GPR effectively as elements. They are
1946 expected to be Micro-coded by most Hardware implementations.
1953 # SVP64 Branch Conditional behaviour
1955 Please note: although similar, SVP64 Branch instructions should be
1956 considered completely separate and distinct from standard scalar
1957 OpenPOWER-approved v3.0B branches. **v3.0B branches are in no way
1958 impacted, altered, changed or modified in any way, shape or form by the
1959 SVP64 Vectorised Variants**.
1961 It is also extremely important to note that Branches are the sole
1962 pseudo-exception in SVP64 to `Scalar Identity Behaviour`. SVP64 Branches
1963 contain additional modes that are useful for scalar operations (i.e. even
1964 when VL=1 or when using single-bit predication).
1968 Scalar 3.0B Branch Conditional operations, `bc`, `bctar` etc. test
1969 a Condition Register. However for parallel processing it is simply
1970 impossible to perform multiple independent branches: the Program
1971 Counter simply cannot branch to multiple destinations based on multiple
1972 conditions. The best that can be done is to test multiple Conditions
1973 and make a decision of a *single* branch, based on analysis of a *Vector*
1974 of CR Fields which have just been calculated from a *Vector* of results.
1976 In 3D Shader binaries, which are inherently parallelised and predicated,
1977 testing all or some results and branching based on multiple tests is
1978 extremely common, and a fundamental part of Shader Compilers. Example:
1979 without such multi-condition test-and-branch, if a predicate mask is
1980 all zeros a large batch of instructions may be masked out to `nop`,
1981 and it would waste CPU cycles to run them. 3D GPU ISAs can test for
1982 this scenario and, with the appropriate predicate-analysis instruction,
1983 jump over fully-masked-out operations, by spotting that *all* Conditions
1986 Unless Branches are aware and capable of such analysis, additional
1987 instructions would be required which perform Horizontal Cumulative
1988 analysis of Vectorised Condition Register Fields, in order to reduce
1989 the Vector of CR Fields down to one single yes or no decision that a
1990 Scalar-only v3.0B Branch-Conditional could cope with. Such instructions
1991 would be unavoidable, required, and costly by comparison to a single
1992 Vector-aware Branch. Therefore, in order to be commercially competitive,
1993 `sv.bc` and other Vector-aware Branch Conditional instructions are a
1994 high priority for 3D GPU (and OpenCL-style) workloads.
1996 Given that Power ISA v3.0B is already quite powerful, particularly
1997 the Condition Registers and their interaction with Branches, there are
1998 opportunities to create extremely flexible and compact Vectorised Branch
1999 behaviour. In addition, the side-effects (updating of CTR, truncation
2000 of VL, described below) make it a useful instruction even if the branch
2001 points to the next instruction (no actual branch).
2005 When considering an "array" of branch-tests, there are four
2006 primarily-useful modes: AND, OR, NAND and NOR of all Conditions.
2007 NAND and NOR may be synthesised from AND and OR by inverting `BO[1]`
2008 which just leaves two modes:
2010 * Branch takes place on the **first** CR Field test to succeed
2011 (a Great Big OR of all condition tests). Exit occurs
2012 on the first **successful** test.
2013 * Branch takes place only if **all** CR field tests succeed:
2014 a Great Big AND of all condition tests. Exit occurs
2015 on the first **failed** test.
2017 Early-exit is enacted such that the Vectorised Branch does not
2018 perform needless extra tests, which will help reduce reads on
2019 the Condition Register file.
2021 *Note: Early-exit is **MANDATORY** (required) behaviour. Branches
2022 **MUST** exit at the first sequentially-encountered failure point,
2023 for exactly the same reasons for which it is mandatory in programming
2024 languages doing early-exit: to avoid damaging side-effects and to provide
2025 deterministic behaviour. Speculative testing of Condition Register
2026 Fields is permitted, as is speculative calculation of CTR, as long as,
2027 as usual in any Out-of-Order microarchitecture, that speculative testing
2028 is cancelled should an early-exit occur. i.e. the speculation must be
2029 "precise": Program Order must be preserved*
2031 Also note that when early-exit occurs in Horizontal-first Mode, srcstep,
2032 dststep etc. are all reset, ready to begin looping from the beginning
2033 for the next instruction. However for Vertical-first Mode srcstep
2034 etc. are incremented "as usual" i.e. an early-exit has no special impact,
2035 regardless of whether the branch occurred or not. This can leave srcstep
2036 etc. in what may be considered an unusual state on exit from a loop and
2037 it is up to the programmer to reset srcstep, dststep etc. to known-good
2038 values *(easily achieved with `setvl`)*.
2040 Additional useful behaviour involves two primary Modes (both of which
2041 may be enabled and combined):
2043 * **VLSET Mode**: identical to Data-Dependent Fail-First Mode
2044 for Arithmetic SVP64 operations, with more
2045 flexibility and a close interaction and integration into the
2046 underlying base Scalar v3.0B Branch instruction.
2047 Truncation of VL takes place around the early-exit point.
2048 * **CTR-test Mode**: gives much more flexibility over when and why
2049 CTR is decremented, including options to decrement if a Condition
2050 test succeeds *or if it fails*.
2052 With these side-effects, basic Boolean Logic Analysis advises that it
2053 is important to provide a means to enact them each based on whether
2054 testing succeeds *or fails*. This results in a not-insignificant number
2055 of additional Mode Augmentation bits, accompanying VLSET and CTR-test
2058 Predicate skipping or zeroing may, as usual with SVP64, be controlled by
2059 `sz`. Where the predicate is masked out and zeroing is enabled, then in
2060 such circumstances the same Boolean Logic Analysis dictates that rather
2061 than testing only against zero, the option to test against one is also
2062 prudent. This introduces a new immediate field, `SNZ`, which works in
2063 conjunction with `sz`.
2065 Vectorised Branches can be used in either SVP64 Horizontal-First or
2066 Vertical-First Mode. Essentially, at an element level, the behaviour
2067 is identical in both Modes, although the `ALL` bit is meaningless in
2068 Vertical-First Mode.
2070 It is also important to bear in mind that, fundamentally, Vectorised
2071 Branch-Conditional is still extremely close to the Scalar v3.0B
2072 Branch-Conditional instructions, and that the same v3.0B Scalar
2073 Branch-Conditional instructions are still *completely separate and
2074 independent*, being unaltered and unaffected by their SVP64 variants in
2075 every conceivable way.
2077 *Programming note: One important point is that SVP64 instructions are
2078 64 bit. (8 bytes not 4). This needs to be taken into consideration
2079 when computing branch offsets: the offset is relative to the start of
2080 the instruction, which **includes** the SVP64 Prefix*
2082 ## Format and fields
2084 With element-width overrides being meaningless for Condition Register
2085 Fields, bits 4 thru 7 of SVP64 RM may be used for additional Mode bits.
2087 SVP64 RM `MODE` (includes repurposing `ELWIDTH` bits 4:5, and
2088 `ELWIDTH_SRC` bits 6-7 for *alternate* uses) for Branch Conditional:
2090 | 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 | 21 | 22 23 | description |
2091 | - | - | - | - | -- | -- | -- | -- | --- |--------|----------------- |
2092 |ALL|SNZ| / | / | SL |SLu | 0 | 0 | / | LRu sz | simple mode |
2093 |ALL|SNZ| / |VSb| SL |SLu | 0 | 1 | VLI | LRu sz | VLSET mode |
2094 |ALL|SNZ|CTi| / | SL |SLu | 1 | 0 | / | LRu sz | CTR-test mode |
2095 |ALL|SNZ|CTi|VSb| SL |SLu | 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode |
2097 Brief description of fields:
2099 * **sz=1** if predication is enabled and `sz=1` and a predicate
2100 element bit is zero, `SNZ` will
2101 be substituted in place of the CR bit selected by `BI`,
2102 as the Condition tested.
2104 normal SVP64 `sz=1` behaviour, where *only* a zero is put in
2105 place of masked-out predicate bits.
2106 * **sz=0** When `sz=0` skipping occurs as usual on
2107 masked-out elements, but unlike all
2108 other SVP64 behaviour which entirely skips an element with
2109 no related side-effects at all, there are certain
2110 special circumstances where CTR
2111 may be decremented. See CTR-test Mode, below.
2112 * **ALL** when set, all branch conditional tests must pass in order for
2113 the branch to succeed. When clear, it is the first sequentially
2114 encountered successful test that causes the branch to succeed.
2115 This is identical behaviour to how programming languages perform
2116 early-exit on Boolean Logic chains.
2117 * **VLI** VLSET is identical to Data-dependent Fail-First mode.
2118 In VLSET mode, VL *may* (depending on `VSb`) be truncated.
2119 If VLI (Vector Length Inclusive) is clear,
2120 VL is truncated to *exclude* the current element, otherwise it is
2121 included. SVSTATE.MVL is not altered: only VL.
2122 * **SL** identical to `LR` except applicable to SVSTATE. If `SL`
2123 is set, SVSTATE is transferred to SVLR (conditionally on
2124 whether `SLu` is set).
2125 * **SLu**: SVSTATE Link Update, like `LRu` except applies to SVSTATE.
2126 * **LRu**: Link Register Update, used in conjunction with LK=1
2127 to make LR update conditional
2128 * **VSb** In VLSET Mode, after testing,
2129 if VSb is set, VL is truncated if the test succeeds. If VSb is clear,
2130 VL is truncated if a test *fails*. Masked-out (skipped)
2131 bits are not considered
2132 part of testing when `sz=0`
2133 * **CTi** CTR inversion. CTR-test Mode normally decrements per element
2134 tested. CTR inversion decrements if a test *fails*. Only relevant
2137 LRu and CTR-test modes are where SVP64 Branches subtly differ from
2138 Scalar v3.0B Branches. `sv.bcl` for example will always update LR,
2139 whereas `sv.bcl/lru` will only update LR if the branch succeeds.
2141 Of special interest is that when using ALL Mode (Great Big AND of all
2142 Condition Tests), if `VL=0`, which is rare but can occur in Data-Dependent
2143 Modes, the Branch will always take place because there will be no failing
2144 Condition Tests to prevent it. Likewise when not using ALL Mode (Great
2145 Big OR of all Condition Tests) and `VL=0` the Branch is guaranteed not
2146 to occur because there will be no *successful* Condition Tests to make
2149 ## Vectorised CR Field numbering, and Scalar behaviour
2151 It is important to keep in mind that just like all SVP64 instructions,
2152 the `BI` field of the base v3.0B Branch Conditional instruction may be
2153 extended by SVP64 EXTRA augmentation, as well as be marked as either
2154 Scalar or Vector. It is also crucially important to keep in mind that for
2155 CRs, SVP64 sequentially increments the CR *Field* numbers. CR *Fields*
2156 are treated as elements, not bit-numbers of the CR *register*.
2158 The `BI` operand of Branch Conditional operations is five bits, in scalar
2159 v3.0B this would select one bit of the 32 bit CR, comprising eight CR
2160 Fields of 4 bits each. In SVP64 there are 16 32 bit CRs, containing
2161 128 4-bit CR Fields. Therefore, the 2 LSBs of `BI` select the bit from
2162 the CR Field (EQ LT GT SO), and the top 3 bits are extended to either
2163 scalar or vector and to select CR Fields 0..127 as specified in SVP64
2164 [[sv/svp64/appendix]].
2166 When the CR Fields selected by SVP64-Augmented `BI` is marked as scalar,
2167 then as the usual SVP64 rules apply: the Vector loop ends at the first
2168 element tested (the first CR *Field*), after taking predication into
2169 consideration. Thus, also as usual, when a predicate mask is given, and
2170 `BI` marked as scalar, and `sz` is zero, srcstep skips forward to the
2171 first non-zero predicated element, and only that one element is tested.
2173 In other words, the fact that this is a Branch Operation (instead of an
2174 arithmetic one) does not result, ultimately, in significant changes as
2175 to how SVP64 is fundamentally applied, except with respect to:
2177 * the unique properties associated with conditionally
2178 changing the Program Counter (aka "a Branch"), resulting in early-out
2182 Both are outlined below, in later sections.
2184 ## Horizontal-First and Vertical-First Modes
2186 In SVP64 Horizontal-First Mode, the first failure in ALL mode (Great Big
2187 AND) results in early exit: no more updates to CTR occur (if requested);
2188 no branch occurs, and LR is not updated (if requested). Likewise for
2189 non-ALL mode (Great Big Or) on first success early exit also occurs,
2190 however this time with the Branch proceeding. In both cases the testing
2191 of the Vector of CRs should be done in linear sequential order (or in
2192 REMAP re-sequenced order): such that tests that are sequentially beyond
2193 the exit point are *not* carried out. (*Note: it is standard practice
2194 in Programming languages to exit early from conditional tests, however a
2195 little unusual to consider in an ISA that is designed for Parallel Vector
2196 Processing. The reason is to have strictly-defined guaranteed behaviour*)
2198 In Vertical-First Mode, setting the `ALL` bit results in `UNDEFINED`
2199 behaviour. Given that only one element is being tested at a time in
2200 Vertical-First Mode, a test designed to be done on multiple bits is
2203 ## Description and Modes
2205 Predication in both INT and CR modes may be applied to `sv.bc` and other
2206 SVP64 Branch Conditional operations, exactly as they may be applied to
2207 other SVP64 operations. When `sz` is zero, any masked-out Branch-element
2208 operations are not included in condition testing, exactly like all other
2209 SVP64 operations, *including* side-effects such as potentially updating
2210 LR or CTR, which will also be skipped. There is *one* exception here,
2211 which is when `BO[2]=0, sz=0, CTR-test=0, CTi=1` and the relevant element
2212 predicate mask bit is also zero: under these special circumstances CTR
2213 will also decrement.
2215 When `sz` is non-zero, this normally requests insertion of a zero in
2216 place of the input data, when the relevant predicate mask bit is zero.
2217 This would mean that a zero is inserted in place of `CR[BI+32]` for
2218 testing against `BO`, which may not be desirable in all circumstances.
2219 Therefore, an extra field is provided `SNZ`, which, if set, will insert
2220 a **one** in place of a masked-out element, instead of a zero.
2222 (*Note: Both options are provided because it is useful to deliberately
2223 cause the Branch-Conditional Vector testing to fail at a specific point,
2224 controlled by the Predicate mask. This is particularly useful in `VLSET`
2225 mode, which will truncate SVSTATE.VL at the point of the first failed
2228 Normally, CTR mode will decrement once per Condition Test, resulting under
2229 normal circumstances that CTR reduces by up to VL in Horizontal-First
2230 Mode. Just as when v3.0B Branch-Conditional saves at least one instruction
2231 on tight inner loops through auto-decrementation of CTR, likewise it
2232 is also possible to save instruction count for SVP64 loops in both
2233 Vertical-First and Horizontal-First Mode, particularly in circumstances
2234 where there is conditional interaction between the element computation
2235 and testing, and the continuation (or otherwise) of a given loop. The
2236 potential combinations of interactions is why CTR testing options have
2239 Also, the unconditional bit `BO[0]` is still relevant when Predication
2240 is applied to the Branch because in `ALL` mode all nonmasked bits have
2241 to be tested, and when `sz=0` skipping occurs. Even when VLSET mode is
2242 not used, CTR may still be decremented by the total number of nonmasked
2243 elements, acting in effect as either a popcount or cntlz depending
2244 on which mode bits are set. In short, Vectorised Branch becomes an
2245 extremely powerful tool.
2247 **Micro-Architectural Implementation Note**: *when implemented on top
2248 of a Multi-Issue Out-of-Order Engine it is possible to pass a copy of
2249 the predicate and the prerequisite CR Fields to all Branch Units, as
2250 well as the current value of CTR at the time of multi-issue, and for
2251 each Branch Unit to compute how many times CTR would be subtracted,
2252 in a fully-deterministic and parallel fashion. A SIMD-based Branch
2253 Unit, receiving and processing multiple CR Fields covered by multiple
2254 predicate bits, would do the exact same thing. Obviously, however, if
2255 CTR is modified within any given loop (mtctr) the behaviour of CTR is
2256 no longer deterministic.*
2258 ### Link Register Update
2260 For a Scalar Branch, unconditional updating of the Link Register LR
2261 is useful and practical. However, if a loop of CR Fields is tested,
2262 unconditional updating of LR becomes problematic.
2264 For example when using `bclr` with `LRu=1,LK=0` in Horizontal-First Mode,
2265 LR's value will be unconditionally overwritten after the first element,
2266 such that for execution (testing) of the second element, LR has the value
2267 `CIA+8`. This is covered in the `bclrl` example, in a later section.
2269 The addition of a LRu bit modifies behaviour in conjunction with LK,
2272 * `sv.bc` When LRu=0,LK=0, Link Register is not updated
2273 * `sv.bcl` When LRu=0,LK=1, Link Register is updated unconditionally
2274 * `sv.bcl/lru` When LRu=1,LK=1, Link Register will
2275 only be updated if the Branch Condition fails.
2276 * `sv.bc/lru` When LRu=1,LK=0, Link Register will only be updated if
2277 the Branch Condition succeeds.
2279 This avoids destruction of LR during loops (particularly Vertical-First
2282 **SVLR and SVSTATE**
2284 For precisely the reasons why `LK=1` was added originally to the Power
2285 ISA, with SVSTATE being a peer of the Program Counter it becomes necessary
2286 to also add an SVLR (SVSTATE Link Register) and corresponding control bits
2291 Where a standard Scalar v3.0B branch unconditionally decrements CTR when
2292 `BO[2]` is clear, CTR-test Mode introduces more flexibility which allows
2293 CTR to be used for many more types of Vector loops constructs.
2295 CTR-test mode and CTi interaction is as follows: note that `BO[2]`
2296 is still required to be clear for CTR decrements to be considered,
2297 exactly as is the case in Scalar Power ISA v3.0B
2299 * **CTR-test=0, CTi=0**: CTR decrements on a per-element basis
2300 if `BO[2]` is zero. Masked-out elements when `sz=0` are
2301 skipped (i.e. CTR is *not* decremented when the predicate
2302 bit is zero and `sz=0`).
2303 * **CTR-test=0, CTi=1**: CTR decrements on a per-element basis
2304 if `BO[2]` is zero and a masked-out element is skipped
2305 (`sz=0` and predicate bit is zero). This one special case is the
2306 **opposite** of other combinations, as well as being
2307 completely different from normal SVP64 `sz=0` behaviour)
2308 * **CTR-test=1, CTi=0**: CTR decrements on a per-element basis
2309 if `BO[2]` is zero and the Condition Test succeeds.
2310 Masked-out elements when `sz=0` are skipped (including
2311 not decrementing CTR)
2312 * **CTR-test=1, CTi=1**: CTR decrements on a per-element basis
2313 if `BO[2]` is zero and the Condition Test *fails*.
2314 Masked-out elements when `sz=0` are skipped (including
2315 not decrementing CTR)
2317 `CTR-test=0, CTi=1, sz=0` requires special emphasis because it is the
2318 only time in the entirety of SVP64 that has side-effects when
2319 a predicate mask bit is clear. **All** other SVP64 operations
2320 entirely skip an element when sz=0 and a predicate mask bit is zero.
2321 It is also critical to emphasise that in this unusual mode,
2322 no other side-effects occur: **only** CTR is decremented, i.e. the
2323 rest of the Branch operation is skipped.
2327 VLSET Mode truncates the Vector Length so that subsequent instructions
2328 operate on a reduced Vector Length. This is similar to Data-dependent
2329 Fail-First and LD/ST Fail-First, where for VLSET the truncation occurs
2330 at the Branch decision-point.
2332 Interestingly, due to the side-effects of `VLSET` mode it is actually
2333 useful to use Branch Conditional even to perform no actual branch
2334 operation, i.e to point to the instruction after the branch. Truncation of
2335 VL would thus conditionally occur yet control flow alteration would not.
2337 `VLSET` mode with Vertical-First is particularly unusual. Vertical-First
2338 is designed to be used for explicit looping, where an explicit call to
2339 `svstep` is required to move both srcstep and dststep on to the next
2340 element, until VL (or other condition) is reached. Vertical-First Looping
2341 is expected (required) to terminate if the end of the Vector, VL, is
2342 reached. If however that loop is terminated early because VL is truncated,
2343 VLSET with Vertical-First becomes meaningless. Resolving this would
2344 require two branches: one Conditional, the other branching unconditionally
2345 to create the loop, where the Conditional one jumps over it.
2347 Therefore, with `VSb`, the option to decide whether truncation should
2348 occur if the branch succeeds *or* if the branch condition fails allows
2349 for the flexibility required. This allows a Vertical-First Branch to
2350 *either* be used as a branch-back (loop) *or* as part of a conditional
2351 exit or function call from *inside* a loop, and for VLSET to be integrated
2352 into both types of decision-making.
2354 In the case of a Vertical-First branch-back (loop), with `VSb=0` the
2355 branch takes place if success conditions are met, but on exit from that
2356 loop (branch condition fails), VL will be truncated. This is extremely
2359 `VLSET` mode with Horizontal-First when `VSb=0` is still useful, because
2360 it can be used to truncate VL to the first predicated (non-masked-out)
2363 The truncation point for VL, when VLi is clear, must not include skipped
2364 elements that preceded the current element being tested. Example:
2365 `sz=0, VLi=0, predicate mask = 0b110010` and the Condition Register
2366 failure point is at CR Field element 4.
2368 * Testing at element 0 is skipped because its predicate bit is zero
2369 * Testing at element 1 passed
2370 * Testing elements 2 and 3 are skipped because their
2371 respective predicate mask bits are zero
2372 * Testing element 4 fails therefore VL is truncated to **2**
2373 not 4 due to elements 2 and 3 being skipped.
2375 If `sz=1` in the above example *then* VL would have been set to 4 because
2376 in non-zeroing mode the zero'd elements are still effectively part of the
2377 Vector (with their respective elements set to `SNZ`)
2379 If `VLI=1` then VL would be set to 5 regardless of sz, due to being inclusive
2380 of the element actually being tested.
2382 ### VLSET and CTR-test combined
2384 If both CTR-test and VLSET Modes are requested, it is important to
2385 observe the correct order. What occurs depends on whether VLi is enabled,
2386 because VLi affects the length, VL.
2388 If VLi (VL truncate inclusive) is set:
2390 1. compute the test including whether CTR triggers
2391 2. (optionally) decrement CTR
2392 3. (optionally) truncate VL (VSb inverts the decision)
2393 4. decide (based on step 1) whether to terminate looping
2394 (including not executing step 5)
2395 5. decide whether to branch.
2397 If VLi is clear, then when a test fails that element
2398 and any following it
2399 should **not** be considered part of the Vector. Consequently:
2401 1. compute the branch test including whether CTR triggers
2402 2. if the test fails against VSb, truncate VL to the *previous*
2403 element, and terminate looping. No further steps executed.
2404 3. (optionally) decrement CTR
2405 4. decide whether to branch.
2407 ## Boolean Logic combinations
2409 In a Scalar ISA, Branch-Conditional testing even of vector results may be
2410 performed through inversion of tests. NOR of all tests may be performed
2411 by inversion of the scalar condition and branching *out* from the scalar
2412 loop around elements, using scalar operations.
2414 In a parallel (Vector) ISA it is the ISA itself which must perform
2415 the prerequisite logic manipulation. Thus for SVP64 there are an
2416 extraordinary number of nesessary combinations which provide completely
2417 different and useful behaviour. Available options to combine:
2419 * `BO[0]` to make an unconditional branch would seem irrelevant if
2420 it were not for predication and for side-effects (CTR Mode
2422 * Enabling CTR-test Mode and setting `BO[2]` can still result in the
2424 taking place, not because the Condition Test itself failed, but
2425 because CTR reached zero **because**, as required by CTR-test mode,
2426 CTR was decremented as a **result** of Condition Tests failing.
2427 * `BO[1]` to select whether the CR bit being tested is zero or nonzero
2428 * `R30` and `~R30` and other predicate mask options including CR and
2429 inverted CR bit testing
2430 * `sz` and `SNZ` to insert either zeros or ones in place of masked-out
2432 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
2433 `OR` of all tests, respectively.
2434 * Predicate Mask bits, which combine in effect with the CR being
2436 * Inversion of Predicate Masks (`~r3` instead of `r3`, or using
2437 `NE` rather than `EQ`) which results in an additional
2438 level of possible ANDing, ORing etc. that would otherwise
2439 need explicit instructions.
2441 The most obviously useful combinations here are to set `BO[1]` to zero
2442 in order to turn `ALL` into Great-Big-NAND and `ANY` into Great-Big-NOR.
2443 Other Mode bits which perform behavioural inversion then have to work
2444 round the fact that the Condition Testing is NOR or NAND. The alternative
2445 to not having additional behavioural inversion (`SNZ`, `VSb`, `CTi`)
2446 would be to have a second (unconditional) branch directly after the first,
2447 which the first branch jumps over. This contrivance is avoided by the
2448 behavioural inversion bits.
2450 ## Pseudocode and examples
2452 Please see the SVP64 appendix regarding CR bit ordering and for
2453 the definition of `CR{n}`
2455 For comparative purposes this is a copy of the v3.0B `bc` pseudocode
2458 if (mode_is_64bit) then M <- 0
2460 if ¬BO[2] then CTR <- CTR - 1
2461 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2462 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2463 if ctr_ok & cond_ok then
2464 if AA then NIA <-iea EXTS(BD || 0b00)
2465 else NIA <-iea CIA + EXTS(BD || 0b00)
2466 if LK then LR <-iea CIA + 4
2469 Simplified pseudocode including LRu and CTR skipping, which illustrates
2470 clearly that SVP64 Scalar Branches (VL=1) are **not** identical to
2471 v3.0B Scalar Branches. The key areas where differences occur are the
2472 inclusion of predication (which can still be used when VL=1), in when and
2473 why CTR is decremented (CTRtest Mode) and whether LR is updated (which
2474 is unconditional in v3.0B when LK=1, and conditional in SVP64 when LRu=1).
2476 Inline comments highlight the fact that the Scalar Branch behaviour and
2477 pseudocode is still clearly visible and embedded within the Vectorised
2481 if (mode_is_64bit) then M <- 0
2483 # the bit of CR to test, if the predicate bit is zero,
2486 if ¬predicate_bit then testbit = SVRMmode.SNZ
2487 # otherwise apart from the override ctr_ok and cond_ok
2488 # are exactly the same
2489 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2490 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2491 if ¬predicate_bit & ¬SVRMmode.sz then
2492 # this is entirely new: CTR-test mode still decrements CTR
2493 # even when predicate-bits are zero
2494 if ¬BO[2] & CTRtest & ¬CTi then
2496 # instruction finishes here
2498 # usual BO[2] CTR-mode now under CTR-test mode as well
2499 if ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) then CTR <- CTR - 1
2500 # new VLset mode, conditional test truncates VL
2501 if VLSET and VSb = (cond_ok & ctr_ok) then
2502 if SVRMmode.VLI then SVSTATE.VL = srcstep+1
2503 else SVSTATE.VL = srcstep
2504 # usual LR is now conditional, but also joined by SVLR
2506 svlr_ok <- SVRMmode.SL
2507 if ctr_ok & cond_ok then
2508 if AA then NIA <-iea EXTS(BD || 0b00)
2509 else NIA <-iea CIA + EXTS(BD || 0b00)
2510 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2511 if SVRMmode.SLu then svlr_ok <- ¬svlr_ok
2512 if lr_ok then LR <-iea CIA + 4
2513 if svlr_ok then SVLR <- SVSTATE
2516 Below is the pseudocode for SVP64 Branches, which is a little less
2517 obvious but identical to the above. The lack of obviousness is down to
2518 the early-exit opportunities.
2520 Effective pseudocode for Horizontal-First Mode:
2523 if (mode_is_64bit) then M <- 0
2525 cond_ok = not SVRMmode.ALL
2526 for srcstep in range(VL):
2527 # select predicate bit or zero/one
2528 if predicate[srcstep]:
2529 # get SVP64 extended CR field 0..127
2530 SVCRf = SVP64EXTRA(BI>>2)
2532 testbit = CRbits[BI & 0b11]
2533 # testbit = CR[BI+32+srcstep*4]
2534 else if not SVRMmode.sz:
2535 # inverted CTR test skip mode
2536 if ¬BO[2] & CTRtest & ¬CTI then
2538 continue # skip to next element
2540 testbit = SVRMmode.SNZ
2541 # actual element test here
2542 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2543 el_cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2544 # check if CTR dec should occur
2546 if CTRtest & (el_cond_ok ^ CTi) then
2548 if ctrdec then CTR <- CTR - 1
2551 cond_ok &= (el_cond_ok & ctr_ok)
2553 cond_ok |= (el_cond_ok & ctr_ok)
2554 # test for VL to be set (and exit)
2555 if VLSET and VSb = (el_cond_ok & ctr_ok) then
2556 if SVRMmode.VLI then SVSTATE.VL = srcstep+1
2557 else SVSTATE.VL = srcstep
2560 if SVRMmode.ALL != (el_cond_ok & ctr_ok):
2562 # SVP64 rules about Scalar registers still apply!
2565 # loop finally done, now test if branch (and update LR)
2567 svlr_ok <- SVRMmode.SL
2569 if AA then NIA <-iea EXTS(BD || 0b00)
2570 else NIA <-iea CIA + EXTS(BD || 0b00)
2571 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2572 if SVRMmode.SLu then svlr_ok <- ¬svlr_ok
2573 if lr_ok then LR <-iea CIA + 4
2574 if svlr_ok then SVLR <- SVSTATE
2577 Pseudocode for Vertical-First Mode:
2580 # get SVP64 extended CR field 0..127
2581 SVCRf = SVP64EXTRA(BI>>2)
2583 # select predicate bit or zero/one
2584 if predicate[srcstep]:
2585 if BRc = 1 then # CR0 vectorised
2586 CR{SVCRf+srcstep} = CRbits
2587 testbit = CRbits[BI & 0b11]
2588 else if not SVRMmode.sz:
2589 # inverted CTR test skip mode
2590 if ¬BO[2] & CTRtest & ¬CTI then
2592 SVSTATE.srcstep = new_srcstep
2593 exit # no branch testing
2595 testbit = SVRMmode.SNZ
2596 # actual element test here
2597 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
2598 # test for VL to be set (and exit)
2599 if VLSET and cond_ok = VSb then
2601 SVSTATE.VL = new_srcstep+1
2603 SVSTATE.VL = new_srcstep
2606 ### Example Shader code
2609 // assume f() g() or h() modify a and/or b
2619 which compiles to something like:
2624 pred loop_pred = a > 2;
2625 // loop continues while any of a elements greater than 2
2626 while(loop_pred.any()) {
2627 // vector of predicate bits
2628 pred if_pred = loop_pred & (b < 5);
2629 // only call f() if at least 1 bit set
2634 // loop mask ANDs with inverted if-test
2635 pred else_pred = loop_pred & ~if_pred;
2636 // only call g() if at least 1 bit set
2637 if(else_pred.any()) {
2644 which will end up as:
2647 # start from while loop test point
2650 sv.cmpi CR80.v, b.v, 5 # vector compare b into CR64 Vector
2651 sv.bc/m=r30/~ALL/sz CR80.v.LT skip_f # skip when none
2652 # only calculate loop_pred & pred_b because needed in f()
2653 sv.crand CR80.v.SO, CR60.v.GT, CR80.V.LT # if = loop & pred_b
2656 # illustrate inversion of pred_b. invert r30, test ALL
2657 # rather than SOME, but masked-out zero test would FAIL,
2658 # therefore masked-out instead is tested against 1 not 0
2659 sv.bc/m=~r30/ALL/SNZ CR80.v.LT skip_g
2660 # else = loop & ~pred_b, need this because used in g()
2661 sv.crternari(A&~B) CR80.v.SO, CR60.v.GT, CR80.V.LT
2664 # conditionally call h(r30) if any loop pred set
2665 sv.bclr/m=r30/~ALL/sz BO[1]=1 h()
2667 sv.cmpi CR60.v a.v, 2 # vector compare a into CR60 vector
2668 sv.crweird r30, CR60.GT # transfer GT vector to r30
2669 sv.bc/m=r30/~ALL/sz BO[1]=1 while_loop
2675 show why LRu would be useful in a loop. Imagine the following
2679 for (int i = 0; i < 8; i++) {
2684 Under these circumstances exiting from the loop is not only based on
2685 CTR it has become conditional on a CR result. Thus it is desirable that
2686 NIA *and* LR only be modified if the conditions are met
2688 v3.0 pseudocode for `bclrl`:
2691 if (mode_is_64bit) then M <- 0
2693 if ¬BO[2] then CTR <- CTR - 1
2694 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
2695 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2696 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
2697 if LK then LR <-iea CIA + 4
2700 the latter part for SVP64 `bclrl` becomes:
2706 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2708 if ctr_ok & cond_ok then
2709 NIA <-iea LR[0:61] || 0b00
2710 if SVRMmode.LRu then lr_ok <- ¬lr_ok
2711 if lr_ok then LR <-iea CIA + 4
2712 # if NIA modified exit loop
2715 The reason why should be clear from this being a Vector loop:
2716 unconditional destruction of LR when LK=1 makes `sv.bclrl` ineffective,
2717 because the intention going into the loop is that the branch should be to
2718 the copy of LR set at the *start* of the loop, not half way through it.
2719 However if the change to LR only occurs if the branch is taken then it
2720 becomes a useful instruction.
2722 The following pseudocode should **not** be implemented because it
2723 violates the fundamental principle of SVP64 which is that SVP64 looping
2724 is a thin wrapper around Scalar Instructions. The pseducode below is
2725 more an actual Vector ISA Branch and as such is not at all appropriate:
2731 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
2732 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
2733 # only at the end of looping is LK checked.
2734 # this completely violates the design principle of SVP64
2735 # and would actually need to be a separate (scalar)
2736 # instruction "set LR to CIA+4 but retrospectively"
2737 # which is clearly impossible
2738 if LK then LR <-iea CIA + 4