openpower/sv/rfc/ls011.mdwn

   1 # LD/ST-Update-PostIncrement
   2
   3 TODO (key stub notes below)
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
   6
   7 The following instructions are proposed to be added in EXT2xx,
   8 duplicating LD/ST-Update functionality but moving the update
   9 of RA to *after* the Memory operation.  These types of
  10 instructions are already present in x86 (sort-of).
  11
  12 * x86 chose that store should be pre-indexed and load should be post-indexed
  13 * Power ISA chose everything to be pre-indexed
  14
  15 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
  16
  17
  18 ```
  19 # LD/ST-Postincrement
  20 lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  21 lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  22 lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  23 lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  24 lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  25 lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  26 lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  27 lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  28 lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  29 ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  30 ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  31 stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  32 stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  33 sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  34 sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  35 stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  36 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  37 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  38 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  39 # FP LD/ST-Postincrement
  40 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  41 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  42 lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  43 lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  44 stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  45 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  46 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  47 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  48 ```
  49
  50 # Example
  51
  52 ** Load Byte and Zero with Post-Update**
  53
  54 D-Form
  55
  56 * lbzup RT,D(RA)
  57
  58 Pseudo-code:
  59
  60 ```
  61     EA <- (RA)
  62     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  63     RA <- (RA) + EXTS(D)
  64 ```
  65
  66 Special Registers Altered:
  67
  68 ```
  69     None
  70 ```
  71
  72 where the same pseudocode for `lbzu` is:
  73
  74 ```
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78 ```
  79
  80 [[!tag opf_rfc]]