openpower/sv/rfc/ls011.mdwn

   1 # RFC ls011 LD/ST-Update-PostIncrement
   2
   3 **URLs**:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls011/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/TODO>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 21 Apr 2023.
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.0B
  19
  20 **Books and Section affected**:
  21
  22 ```
  23     Chapter 2 Book I, new Fixed-Point Load / Store Sections 3.3.2 3.3.3
  24     Chapter 4 Book I, new Floating-Point Load / Store Sections 4.6.2 4.6.3
  25 ```
  26
  27 **Summary**
  28
  29 ```
  30     TODO
  31 ```
  32
  33 **Submitter**: Luke Leighton (Libre-SOC)
  34
  35 **Requester**: Libre-SOC
  36
  37 **Impact on processor**:
  38
  39 ```
  40     TODO
  41 ```
  42
  43 **Impact on software**:
  44
  45 ```
  46     Requires support for new instructions in assembler, debuggers, and related tools.
  47     Reduces instructions in hot-loops
  48 ```
  49
  50 **Keywords**:
  51
  52 ```
  53
  54 ```
  55
  56 **Motivation**
  57
  58
  59
  60 **Notes and Observations**:
  61
  62
  63
  64 **Changes**
  65
  66 Add the following entries to:
  67
  68 * A new "Vector Looping" Book
  69 * New Vector-Looping Chapters
  70 * New Vector-Looping Appendices
  71
  72 [[!tag opf_rfc]]
  73
  74 --------
  75
  76 \newpage{}
  77
  78 TODO (key stub notes below)
  79
  80
  81
  82 The following instructions are proposed to be added in EXT2xx,
  83 duplicating LD/ST-Update functionality but moving the update
  84 of RA to *after* the Memory operation.  These types of
  85 instructions are already present in x86 (sort-of).
  86
  87 * x86 chose that store should be pre-indexed and load should be post-indexed
  88 * Power ISA chose everything to be pre-indexed
  89 * Motorola 68000 (decades old) has pre- and post- indexed
  90
  91 <https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
  92
  93 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
  94
  95 The LD/ST-Immediate-Post-Increment instructions are all Primary
  96 Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
  97 are all effectively 9-bit XO and consequently may easily
  98 fit into one single Primary Opcode.  EXT2xx is recommended.
  99
 100 One alternative idea is that bit 31 could be allocated (retrospectively)
 101 to Post-Increment.  Although it may be too late for Scalar Power ISA
 102 it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
 103 but this risks creating a non-Orthogonal ISA.
 104
 105
 106
 107 ```
 108 # LD/ST-Postincrement
 109 lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 110 lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 111 lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 112 lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 113 lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 114 lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 115 lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 116 lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 117 lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 118 ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 119 ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 120 stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 121 stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 122 sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 123 sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 124 stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 125 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 126 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 127 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 128
 129 # FP LD/ST-Postincrement
 130 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 131 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 132 lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 133 lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 134 stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 135 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 136 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 137 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 138
 139 # LD/ST-Shifted-Postincrement
 140 lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 141 lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 142 lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 143 lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 144 lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 145 lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 146 stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 147 sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 148 stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 149 stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 150
 151 # FP LD/ST-Shifted-Postincrement
 152 lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 153 lfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 154 stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 155 stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 156
 157 ```
 158
 159 # Example
 160
 161 Here is an annotated example where the pseudo-code changes to
 162 just use `RA` as the address, otherwise remaining the same.
 163 No actual change to the Effective Address computation itself
 164 occurs, in any of the Post-Update instructions.
 165
 166 **Load Byte and Zero with Post-Update**
 167
 168 D-Form
 169
 170 * lbzup RT,D(RA)
 171
 172 Pseudo-code:
 173
 174 ```
 175     EA <- (RA)                           # EA just RA
 176     RT <- ([0] * (XLEN-8)) || MEM(EA, 1) # then load
 177     RA <- (RA) + EXTS(D)                 # then update RA after
 178 ```
 179
 180 Special Registers Altered:
 181
 182 ```
 183     None
 184 ```
 185
 186 where the same pseudocode for `lbzu` is:
 187
 188 ```
 189     EA <- (RA) + EXTS(D)                  # EA includes D
 190     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)  # load from RA+D
 191     RA <- EA                              # and update RA
 192 ```
 193 -----
 194
 195 \newpage{}
 196
 197 # Fixed-point Load with Post-Update
 198
 199 Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1
 200
 201 ## Load Byte and Zero with Post-Update
 202
 203 D-Form
 204
 205 ```
 206     |0     |6   |9  |10 |11   |16      |31 |
 207     | PO   |    RT      |   RA|   D        |
 208 ```
 209
 210 * lbzup RT,D(RA)
 211
 212 Pseudo-code:
 213
 214 ```
 215     EA <- (RA)
 216     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 217     RA <- (RA) + EXTS(D)
 218 ```
 219
 220 Let the effective address (EA) be (RA|0).
 221 The byte in storage addressed by EA is loaded into
 222 RT[56:63]. RT[0:55] are set to 0.
 223
 224 The sum (RA|0)+D is placed into register RA.
 225
 226 If RA=0 or RA=RT, the instruction form is invalid.
 227
 228 Special Registers Altered:
 229
 230     None
 231
 232 ## Load Byte and Zero with Post-Update Indexed
 233
 234 X-Form
 235
 236 ```
 237     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 238     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 239 ```
 240
 241 * lbzupx RT,RA,RB
 242
 243 Pseudo-code:
 244
 245 ```
 246     EA <- (RA)
 247     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 248     RA <- (RA) + (RB)
 249 ```
 250
 251 Let the effective address (EA) be (RA).
 252 The byte in storage addressed by EA is loaded into
 253 RT[56:63]. RT[0:55] are set to 0.
 254
 255 The sum (RA)+(RB) is placed into register RA.
 256
 257 If RA=0 or RA=RT, the instruction form is invalid.
 258
 259 Special Registers Altered:
 260
 261     None
 262
 263 ## Load Halfword and Zero with Post-Update
 264
 265 D-Form
 266
 267 ```
 268     |0     |6   |9  |10 |11   |16      |31 |
 269     | PO   |    RT      |   RA|   D        |
 270 ```
 271
 272 * lhzup RT,D(RA)
 273
 274 Pseudo-code:
 275
 276 ```
 277     EA <- (RA)
 278     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 279     RA <- (RA) + EXTS(D)
 280 ```
 281
 282 Let the effective address (EA) be (RA|0).
 283 The halfword in storage addressed by EA is loaded into
 284 RT[48:63]. RT[0:47] are set to 0.
 285
 286 The sum (RA|0)+D is placed into register RA.
 287
 288 If RA=0 or RA=RT, the instruction form is invalid.
 289
 290 Special Registers Altered:
 291
 292     None
 293
 294 ## Load Halfword and Zero with Post-Update Indexed
 295
 296 X-Form
 297
 298 ```
 299     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 300     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 301 ```
 302
 303 * lhzupx RT,RA,RB
 304
 305 Pseudo-code:
 306
 307 ```
 308     EA <- (RA)
 309     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 310     RA <- (RA) + (RB)
 311 ```
 312
 313 Let the effective address (EA) be (RA).
 314 The halfword in storage addressed by EA is loaded into
 315 RT[48:63]. RT[0:47] are set to 0.
 316
 317 The sum (RA)+(RB) is placed into register RA.
 318
 319 If RA=0 or RA=RT, the instruction form is invalid.
 320
 321 Special Registers Altered:
 322
 323     None
 324
 325 ## Load Halfword Algebraic with Post-Update
 326
 327 D-Form
 328
 329 ```
 330     |0     |6   |9  |10 |11   |16      |31 |
 331     | PO   |    RT      |   RA|   D        |
 332 ```
 333
 334 * lhaup RT,D(RA)
 335
 336 Pseudo-code:
 337
 338 ```
 339     EA <- (RA)
 340     RT <- EXTS(MEM(EA, 2))
 341     RA <- (RA) + EXTS(D)
 342 ```
 343
 344 Special Registers Altered:
 345
 346     None
 347
 348 ## Load Halfword Algebraic with Post-Update Indexed
 349
 350 X-Form
 351
 352 ```
 353     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 354     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 355 ```
 356
 357 * lhaupx RT,RA,RB
 358
 359 Pseudo-code:
 360
 361 ```
 362     EA <- (RA)
 363     RT <- EXTS(MEM(EA, 2))
 364     RA <- (RA) + (RB)
 365 ```
 366
 367 Special Registers Altered:
 368
 369     None
 370
 371 ## Load Word and Zero with Post-Update
 372
 373 D-Form
 374
 375 ```
 376     |0     |6   |9  |10 |11   |16      |31 |
 377     | PO   |    RT      |   RA|   D        |
 378 ```
 379
 380 * lwzup RT,D(RA)
 381
 382 Pseudo-code:
 383
 384 ```
 385     EA <- (RA)
 386     RT <- [0]*32 || MEM(EA, 4)
 387     RA <- (RA) + EXTS(D)
 388 ```
 389
 390 Let the effective address (EA) be (RA|0).
 391 The word in storage addressed by EA is loaded into
 392 RT[32:63]. RT[0:31] are set to 0.
 393
 394 The sum (RA|0)+D is placed into register RA.
 395
 396 If RA=0 or RA=RT, the instruction form is invalid.
 397
 398 Special Registers Altered:
 399
 400     None
 401
 402 ## Load Word and Zero with Post-Update Indexed
 403
 404 X-Form
 405
 406 ```
 407     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 408     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 409 ```
 410
 411 * lwzupx RT,RA,RB
 412
 413 Pseudo-code:
 414
 415 ```
 416     EA <- (RA)
 417     RT <- [0] * 32 || MEM(EA, 4)
 418     RA <- (RA) + (RB)
 419 ```
 420
 421 Let the effective address (EA) be (RA).
 422 The word in storage addressed by EA is loaded into
 423 RT[32:63]. RT[0:31] are set to 0.
 424
 425 The sum (RA)+(RB) is placed into register RA.
 426
 427 If RA=0 or RA=RT, the instruction form is invalid.
 428
 429 Special Registers Altered:
 430
 431     None
 432
 433 ## Load Word Algebraic with Post-Update Indexed
 434
 435 X-Form
 436
 437 ```
 438     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 439     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 440 ```
 441
 442 * lwaupx RT,RA,RB
 443
 444 Pseudo-code:
 445
 446 ```
 447     EA <- (RA)
 448     RT <- EXTS(MEM(EA, 4))
 449     RA <- (RA) + (RB)
 450 ```
 451
 452 Special Registers Altered:
 453
 454     None
 455
 456 ## Load Doubleword with Post-Update Indexed
 457
 458 DS-Form
 459
 460 * ldup RT,DS(RA)
 461
 462 Pseudo-code:
 463
 464 ```
 465     EA <- (RA)
 466     RT <- MEM(EA, 8)
 467     RA <- (RA) + EXTS(DS || 0b00)
 468 ```
 469
 470 Special Registers Altered:
 471
 472     None
 473
 474 ## Load Doubleword with Post-Update Indexed
 475
 476 X-Form
 477
 478 ```
 479     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 480     | PO   |       RT      |    RA       |    RB       |   XO |  / |
 481 ```
 482
 483 * ldupx RT,RA,RB
 484
 485 Pseudo-code:
 486
 487 ```
 488     EA <- (RA)
 489     RT <- MEM(EA, 8)
 490     RA <- (RA) + (RB)
 491 ```
 492
 493 Special Registers Altered:
 494
 495     None
 496
 497 -----
 498
 499 \newpage{}
 500
 501 # Fixed-Point Store Post-Update
 502
 503 Add the following as a new section in Fixed-Point Store, Book I
 504
 505 ## Store Byte with Update
 506
 507 D-Form
 508
 509 ```
 510     |0     |6   |9  |10 |11   |16      |31 |
 511     | PO   |    RT      |   RA|   D        |
 512 ```
 513
 514 * stbup RS,D(RA)
 515
 516 Pseudo-code:
 517
 518 ```
 519     EA <- (RA) + EXTS(D)
 520     ea <- (RA)
 521     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 522     RA <- EA
 523 ```
 524
 525 Special Registers Altered:
 526
 527     None
 528
 529 ## Store Byte with Update Indexed
 530
 531 X-Form
 532
 533 ```
 534     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 535     | PO   |       RS      |    RA       |    RB       |   XO |  / |
 536 ```
 537
 538 * stbupx RS,RA,RB
 539
 540 Pseudo-code:
 541
 542 ```
 543     EA <- (RA) + (RB)
 544     ea <- (RA)
 545     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 546     RA <- EA
 547 ```
 548
 549 Special Registers Altered:
 550
 551     None
 552
 553 ## Store Halfword with Update
 554
 555 D-Form
 556
 557 ```
 558     |0     |6   |9  |10 |11   |16      |31 |
 559     | PO   |    RT      |   RA|   D        |
 560 ```
 561
 562 * sthup RS,D(RA)
 563
 564 Pseudo-code:
 565
 566 ```
 567     EA <- (RA) + EXTS(D)
 568     ea <- (RA)
 569     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 570     RA <- EA
 571 ```
 572
 573 Special Registers Altered:
 574
 575     None
 576
 577 ## Store Halfword with Update Indexed
 578
 579 X-Form
 580
 581 ```
 582     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 583     | PO   |       RS      |    RA       |    RB       |   XO |  / |
 584 ```
 585
 586 * sthupx RS,RA,RB
 587
 588 Pseudo-code:
 589
 590 ```
 591     EA <- (RA) + (RB)
 592     ea <- (RA)
 593     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 594     RA <- EA
 595 ```
 596
 597 Special Registers Altered:
 598
 599     None
 600
 601 ## Store Word with Update
 602
 603 D-Form
 604
 605 ```
 606     |0     |6   |9  |10 |11   |16      |31 |
 607     | PO   |    RT      |   RA|   D        |
 608 ```
 609
 610 * stwup RS,D(RA)
 611
 612 Pseudo-code:
 613
 614 ```
 615     EA <- (RA) + EXTS(D)
 616     ea <- (RA)
 617     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 618     RA <- EA
 619 ```
 620
 621 Special Registers Altered:
 622
 623     None
 624
 625 ## Store Word with Update Indexed
 626
 627 X-Form
 628
 629 ```
 630     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 631     | PO   |       RS      |    RA       |    RB       |   XO |  / |
 632 ```
 633
 634 * stwupx RS,RA,RB
 635
 636 Pseudo-code:
 637
 638 ```
 639     EA <- (RA) + (RB)
 640     ea <- (RA)
 641     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 642     RA <- EA
 643 ```
 644
 645 Special Registers Altered:
 646
 647     None
 648
 649 ## Store Doubleword with Update
 650
 651 DS-Form
 652
 653 * stdup RS,DS(RA)
 654
 655 Pseudo-code:
 656
 657 ```
 658     EA <- (RA) + EXTS(DS || 0b00)
 659     ea <- (RA)
 660     MEM(ea, 8) <- (RS)
 661     RA <- EA
 662 ```
 663
 664 Special Registers Altered:
 665
 666     None
 667
 668 ## Store Doubleword with Update Indexed
 669
 670 X-Form
 671
 672 ```
 673     |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 674     | PO   |       RS      |    RA       |    RB       |   XO |  / |
 675 ```
 676
 677 * stdupx RS,RA,RB
 678
 679 Pseudo-code:
 680
 681 ```
 682     EA <- (RA) + (RB)
 683     ea <- (RA)
 684     MEM(ea, 8) <- (RS)
 685     RA <- EA
 686 ```
 687
 688 Special Registers Altered:
 689
 690     None
 691
 692 [[!tag opf_rfc]]