openpower/sv/rfc/ls011.mdwn

   1 # LD/ST-Update-PostIncrement
   2
   3 TODO (key stub notes below)
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
   6
   7 The following instructions are proposed to be added in EXT2xx,
   8 duplicating LD/ST-Update functionality but moving the update
   9 of RA to *after* the Memory operation.  These types of
  10 instructions are already present in x86 (sort-of).
  11
  12 * x86 chose that store should be pre-indexed and load should be post-indexed
  13 * Power ISA chose everything to be pre-indexed
  14 * Motorola 68000 (decades old) has pre- and post- indexed
  15
  16 <https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
  17
  18 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
  19
  20 The LD/ST-Immediate-Post-Increment instructions are all Primary
  21 Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
  22 are all effectively 9-bit XO and consequently may easily
  23 fit into one single Primary Opcode.  EXT2xx is recommended.
  24
  25 One alternative idea is that bit 31 could be allocated (retrospectively)
  26 to Post-Increment.  Although it may be too late for Scalar Power ISA
  27 it **may** be possible to consider for SVP64Single and/or SVP64-Vector
  28
  29
  30
  31 ```
  32 # LD/ST-Postincrement
  33 lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  34 lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  35 lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  36 lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  37 lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  38 lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  39 lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  40 lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  41 lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  42 ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  43 ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  44 stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  45 stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  46 sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  47 sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  48 stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  49 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  50 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  51 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  52
  53 # FP LD/ST-Postincrement
  54 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  55 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  56 lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  57 lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  58 stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  59 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  60 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  61 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  62
  63 # LD/ST-Shifted-Postincrement
  64 lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  65 lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  66 lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  67 lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  68 lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  69 lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  70 stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  71 sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  72 stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  73 stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  74
  75 # FP LD/ST-Shifted-Postincrement
  76 lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  77 lfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  78 stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  79 stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  80
  81 ```
  82
  83 # Example
  84
  85 ** Load Byte and Zero with Post-Update**
  86
  87 D-Form
  88
  89 * lbzup RT,D(RA)
  90
  91 Pseudo-code:
  92
  93 ```
  94     EA <- (RA)
  95     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  96     RA <- (RA) + EXTS(D)
  97 ```
  98
  99 Special Registers Altered:
 100
 101 ```
 102     None
 103 ```
 104
 105 where the same pseudocode for `lbzu` is:
 106
 107 ```
 108     EA <- (RA) + EXTS(D)
 109     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 110     RA <- EA
 111 ```
 112
 113 [[!tag opf_rfc]]