openpower/sv/rfc/ls011.mdwn

   1 # LD/ST-Update-PostIncrement
   2
   3 TODO (key stub notes below)
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
   6
   7 The following instructions are proposed to be added in EXT2xx,
   8 duplicating LD/ST-Update functionality but moving the update
   9 of RA to *after* the Memory operation.  These types of
  10 instructions are already present in x86 (sort-of).
  11
  12 * x86 chose that store should be pre-indexed and load should be post-indexed
  13 * Power ISA chose everything to be pre-indexed
  14 * Motorola 68000 (decades old) has pre- and post- indexed
  15
  16 <https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
  17
  18 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
  19
  20 The LD/ST-Immediate-Post-Increment instructions are all Primary
  21 Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
  22 are all effectively 9-bit XO and consequently may easily
  23 fit into one single Primary Opcode.  EXT2xx is recommended.
  24
  25 One alternative idea is that bit 31 could be allocated (retrospectively)
  26 to Post-Increment.  Although it may be too late for Scalar Power ISA
  27 it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
  28 but this risks creating a non-Orthogonal ISA.
  29
  30
  31
  32 ```
  33 # LD/ST-Postincrement
  34 lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  35 lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  36 lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  37 lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  38 lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  39 lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  40 lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  41 lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  42 lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  43 ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  44 ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  45 stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  46 stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  47 sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  48 sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  49 stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  50 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  51 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  52 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  53
  54 # FP LD/ST-Postincrement
  55 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  56 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
  57 lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  58 lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
  59 stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  60 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
  61 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  62 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
  63
  64 # LD/ST-Shifted-Postincrement
  65 lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  66 lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  67 lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  68 lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  69 lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  70 lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  71 stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  72 sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  73 stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  74 stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  75
  76 # FP LD/ST-Shifted-Postincrement
  77 lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  78 lfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
  79 stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  80 stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
  81
  82 ```
  83
  84 # Example
  85
  86 Here is an annotated example where the pseudo-code changes to
  87 just use `RA` as the address, otherwise remaining the same.
  88 No actual change to the Effective Address computation itself
  89 occurs, in any of the Post-Update instructions.
  90
  91 ** Load Byte and Zero with Post-Update**
  92
  93 D-Form
  94
  95 * lbzup RT,D(RA)
  96
  97 Pseudo-code:
  98
  99 ```
 100     EA <- (RA)                           # EA just RA
 101     RT <- ([0] * (XLEN-8)) || MEM(EA, 1) # then load
 102     RA <- (RA) + EXTS(D)                 # then update RA after
 103 ```
 104
 105 Special Registers Altered:
 106
 107 ```
 108     None
 109 ```
 110
 111 where the same pseudocode for `lbzu` is:
 112
 113 ```
 114     EA <- (RA) + EXTS(D)                  # EA includes D
 115     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)  # load from RA+D
 116     RA <- EA                              # and update RA
 117 ```
 118 -----
 119
 120 \newpage{}
 121
 122 # Fixed-point Load with Post-Update
 123
 124 Add the following additional Section to Fixed-Point Load Book I
 125
 126 ## Load Byte and Zero with Post-Update
 127
 128 D-Form
 129
 130 * lbzup RT,D(RA)
 131
 132 Pseudo-code:
 133
 134     EA <- (RA)
 135     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 136     RA <- (RA) + EXTS(D)
 137
 138 Special Registers Altered:
 139
 140     None
 141
 142 ## Load Byte and Zero with Post-Update Indexed
 143
 144 X-Form
 145
 146 * lbzupx RT,RA,RB
 147
 148 Pseudo-code:
 149
 150     EA <- (RA)
 151     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 152     RA <- (RA) + (RB)
 153
 154 Special Registers Altered:
 155
 156     None
 157
 158 ## Load Halfword and Zero with Post-Update
 159
 160 D-Form
 161
 162 * lhzup RT,D(RA)
 163
 164 Pseudo-code:
 165
 166     EA <- (RA)
 167     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 168     RA <- (RA) + EXTS(D)
 169
 170 Special Registers Altered:
 171
 172     None
 173
 174 ## Load Halfword and Zero with Post-Update Indexed
 175
 176 X-Form
 177
 178 * lhzupx RT,RA,RB
 179
 180 Pseudo-code:
 181
 182     EA <- (RA)
 183     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 184     RA <- (RA) + (RB)
 185
 186 Special Registers Altered:
 187
 188     None
 189
 190 ## Load Halfword Algebraic with Post-Update
 191
 192 D-Form
 193
 194 * lhaup RT,D(RA)
 195
 196 Pseudo-code:
 197
 198     EA <- (RA)
 199     RT <- EXTS(MEM(EA, 2))
 200     RA <- (RA) + EXTS(D)
 201
 202 Special Registers Altered:
 203
 204     None
 205
 206 ## Load Halfword Algebraic with Post-Update Indexed
 207
 208 X-Form
 209
 210 * lhaupx RT,RA,RB
 211
 212 Pseudo-code:
 213
 214     EA <- (RA)
 215     RT <- EXTS(MEM(EA, 2))
 216     RA <- (RA) + (RB)
 217
 218 Special Registers Altered:
 219
 220     None
 221
 222 ## Load Word and Zero with Post-Update
 223
 224 D-Form
 225
 226 * lwzup RT,D(RA)
 227
 228 Pseudo-code:
 229
 230     EA <- (RA)
 231     RT <- [0]*32 || MEM(EA, 4)
 232     RA <- (RA) + EXTS(D)
 233
 234 Special Registers Altered:
 235
 236     None
 237
 238 ## Load Word and Zero with Post-Update Indexed
 239
 240 X-Form
 241
 242 * lwzupx RT,RA,RB
 243
 244 Pseudo-code:
 245
 246     EA <- (RA)
 247     RT <- [0] * 32 || MEM(EA, 4)
 248     RA <- (RA) + (RB)
 249
 250 Special Registers Altered:
 251
 252     None
 253
 254 ## Load Word Algebraic with Post-Update Indexed
 255
 256 X-Form
 257
 258 * lwaupx RT,RA,RB
 259
 260 Pseudo-code:
 261
 262     EA <- (RA)
 263     RT <- EXTS(MEM(EA, 4))
 264     RA <- (RA) + (RB)
 265
 266 Special Registers Altered:
 267
 268     None
 269
 270 ## Load Doubleword with Post-Update Indexed
 271
 272 DS-Form
 273
 274 * ldup RT,DS(RA)
 275
 276 Pseudo-code:
 277
 278     EA <- (RA)
 279     RT <- MEM(EA, 8)
 280     RA <- (RA) + EXTS(DS || 0b00)
 281
 282 Special Registers Altered:
 283
 284     None
 285
 286 ## Load Doubleword with Post-Update Indexed
 287
 288 X-Form
 289
 290 * ldupx RT,RA,RB
 291
 292 Pseudo-code:
 293
 294     EA <- (RA)
 295     RT <- MEM(EA, 8)
 296     RA <- (RA) + (RB)
 297
 298 Special Registers Altered:
 299
 300     None
 301
 302 -----
 303
 304 \newpage{}
 305
 306 # Fixed-Point Store Post-Update
 307
 308 Add the following as a new section in Fixed-Point Store, Book I
 309
 310 ## Store Byte with Update
 311
 312 D-Form
 313
 314 * stbup RS,D(RA)
 315
 316 Pseudo-code:
 317
 318     EA <- (RA) + EXTS(D)
 319     ea <- (RA)
 320     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 321     RA <- EA
 322
 323 Special Registers Altered:
 324
 325     None
 326
 327 ## Store Byte with Update Indexed
 328
 329 X-Form
 330
 331 * stbupx RS,RA,RB
 332
 333 Pseudo-code:
 334
 335     EA <- (RA) + (RB)
 336     ea <- (RA)
 337     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 338     RA <- EA
 339
 340 Special Registers Altered:
 341
 342     None
 343
 344 ## Store Halfword with Update
 345
 346 D-Form
 347
 348 * sthup RS,D(RA)
 349
 350 Pseudo-code:
 351
 352     EA <- (RA) + EXTS(D)
 353     ea <- (RA)
 354     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 355     RA <- EA
 356
 357 Special Registers Altered:
 358
 359     None
 360
 361 ## Store Halfword with Update Indexed
 362
 363 X-Form
 364
 365 * sthupx RS,RA,RB
 366
 367 Pseudo-code:
 368
 369     EA <- (RA) + (RB)
 370     ea <- (RA)
 371     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 372     RA <- EA
 373
 374 Special Registers Altered:
 375
 376     None
 377
 378 ## Store Word with Update
 379
 380 D-Form
 381
 382 * stwup RS,D(RA)
 383
 384 Pseudo-code:
 385
 386     EA <- (RA) + EXTS(D)
 387     ea <- (RA)
 388     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 389     RA <- EA
 390
 391 Special Registers Altered:
 392
 393     None
 394
 395 ## Store Word with Update Indexed
 396
 397 X-Form
 398
 399 * stwupx RS,RA,RB
 400
 401 Pseudo-code:
 402
 403     EA <- (RA) + (RB)
 404     ea <- (RA)
 405     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 406     RA <- EA
 407
 408 Special Registers Altered:
 409
 410     None
 411
 412 ## Store Doubleword with Update
 413
 414 DS-Form
 415
 416 * stdup RS,DS(RA)
 417
 418 Pseudo-code:
 419
 420     EA <- (RA) + EXTS(DS || 0b00)
 421     ea <- (RA)
 422     MEM(ea, 8) <- (RS)
 423     RA <- EA
 424
 425 Special Registers Altered:
 426
 427     None
 428
 429 ## Store Doubleword with Update Indexed
 430
 431 X-Form
 432
 433 * stdupx RS,RA,RB
 434
 435 Pseudo-code:
 436
 437     EA <- (RA) + (RB)
 438     ea <- (RA)
 439     MEM(ea, 8) <- (RS)
 440     RA <- EA
 441
 442 Special Registers Altered:
 443
 444     None
 445
 446 [[!tag opf_rfc]]