openpower/sv/rfc/ls012.mdwn

   1 # External RFC ls012: Discuss priorities of Libre-SOC Scalar(Vector) ops
   2
   3 * <https://git.openpower.foundation/isa/PowerISA/issues/121>
   4 * <https://bugs.libre-soc.org/show_bug.cgi?id=1051>
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1052>
   6
   7 The purpose of this RFC is to give a full list of the upcoming Scalar
   8 opcodes developed by Libre-SOC, formally agree a priority order, which
   9 ones should be EXT022 Sandbox, and for IBM to get a clear picture of
  10 the Opcode Allocation needs. Worth bearing in mind that every "Defined
  11 Word" may or may not be Vectoriseable, but that every "Defined Word"
  12 should have merits on its own not just when Vectorised.  An example
  13 of a borderline Vectoriseable Defined Word is `mv.swizzle` which
  14 only really becomes high-priority for Vector GPU and HPC Workloads,
  15 but has less merit as a Scalar-only operation.
  16
  17 Power ISA Scalar (SFFS) has not been significantly advanced in 12 years.
  18 With VSX bring 914 instructions and 128-bit it is far too much for any
  19 new team to consider (10 years development effort) and far outside of
  20 Embedded or Tablet/Desktop/Laptop power budgets. Thus bringing Power Scalar
  21 up-to-date to modern standards is a reasonable goal, and the advantage is
  22 that lessons can be learned from other ISAs.
  23
  24 SVP64 Prefixing - also known by the terms "Zero-Overhead-Loop-Prefixing"
  25 as well as "True-Scalable Vector Prefixing" - also literally brings new
  26 dimensions to the Power ISA. Thus when adding new Scalar "Defined Words"
  27 it has to unavoidably be taken into consideration their value when
  28 Vectorised.
  29
  30
  31
  32 Instruction count guide and approximate priority order:
  33
  34 * 6 - SVP64 Management [[ls008]] [[ls009]] [[ls010]]
  35 * 5 - CR weirds [[sv/cr_int_predication]]
  36 * 4 - INT<->FP mv [[ls006]]
  37 * 19 - GPR LD/ST-PostIncrement-Update (saves hugely in hot-loops) [[ls011]]
  38 * ~12 - FPR LD/ST-PostIncrement-Update (ditto) [[ls011]]
  39 * 2 - Float-Load-Immediate (always saves one LD L1/2/3 D-Cache op) [[ls002]]
  40 * 5 - Big-Integer Chained 3-in 2-out (64-bit Carry) [[sv/biginteger]]
  41 * 6 - Bitmanip LUT2/3 operations. high cost high reward [[sv/bitmanip]]
  42 * 1 - fclass (Scalar variant of xvtstdcsp) [[sv/fclass]]
  43 * 5 - Audio-Video [[sv/av_opcodes]]
  44 * 2 - Shift-and-Add (mitigates LD-ST-Shift; Cryptography e.g. twofish)
  45 * 2 - BMI group [[sv/vector_ops]]
  46 * 2 - GPU swizzle [[sv/mv.swizzle]]
  47 * 9 - FP DCT/FFT Butterfly (2/3-in 2-out)
  48 * ~9 Integer DCT/FFT Butterfly
  49 * 18 - Trigonometric (1-arg) [[openpower/transcendentals]]
  50 * 15 - Transcendentals (1-arg) [[openpower/transcendentals]]
  51 * 25 - Transcendentals (2-arg) [[openpower/transcendentals]]
  52
  53 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]
  54
  55 [[!tag opf_rfc]]