5 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturation
6 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47> Parallel Prefix
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=697> Reduce Modes
8 * <https://bugs.libre-soc.org/show_bug.cgi?id=864> parallel prefix simulator
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=809> OV sv.addex discussion
11 This is the appendix to [[sv/svp64]], providing explanations of modes
12 etc. leaving the main svp64 page's primary purpose as outlining the
19 # Partial Implementations
21 It is perfectly legal to implement subsets of SVP64 as long as illegal
22 instruction traps are always raised on unimplemented features,
23 so that soft-emulation is possible,
24 even for future revisions of SVP64. With SVP64 being partly controlled
25 through contextual SPRs, a little care has to be taken.
28 not implemented including reserved ones for future use must raise an illegal
29 instruction trap if read or written. This allows software the
30 opportunity to emulate the context created by the given SPR.
32 See [[sv/compliancy_levels]] for full details.
34 # XER, SO and other global flags
36 Vector systems are expected to be high performance. This is achieved
37 through parallelism, which requires that elements in the vector be
38 independent. XER SO/OV and other global "accumulation" flags (CR.SO) cause
39 Read-Write Hazards on single-bit global resources, having a significant
42 Consequently in SV, XER.SO behaviour is disregarded (including
43 in `cmp` instructions). XER.SO is not read, but XER.OV may be written,
44 breaking the Read-Modify-Write Hazard Chain that complicates
45 microarchitectural implementations.
46 This includes when `scalar identity behaviour` occurs. If precise
47 OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1
48 instructions should be used without an SV Prefix.
50 TODO jacob add about OV https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-large-integer-arithmetic-paper.pdf
52 Of note here is that XER.SO and OV may already be disregarded in the
53 Power ISA v3.0/1 SFFS (Scalar Fixed and Floating) Compliancy Subset.
54 SVP64 simply makes it mandatory to disregard XER.SO even for other Subsets,
55 but only for SVP64 Prefixed Operations.
57 XER.CA/CA32 on the other hand is expected and required to be implemented
58 according to standard Power ISA Scalar behaviour. Interestingly, due
59 to SVP64 being in effect a hardware for-loop around Scalar instructions
60 executing in precise Program Order, a little thought shows that a Vectorised
61 Carry-In-Out add is in effect a Big Integer Add, taking a single bit Carry In
62 and producing, at the end, a single bit Carry out. High performance
63 implementations may exploit this observation to deploy efficient
64 Parallel Carry Lookahead.
66 # assume VL=4, this results in 4 sequential ops (below)
67 sv.adde r0.v, r4.v, r8.v
69 # instructions that get executed in backend hardware:
70 adde r0, r4, r8 # takes carry-in, produces carry-out
71 adde r1, r5, r9 # takes carry from previous
73 adde r3, r7, r11 # likewise
75 It can clearly be seen that the carry chains from one
76 64 bit add to the next, the end result being that a
77 256-bit "Big Integer Add with Carry" has been performed, and that
78 CA contains the 257th bit. A one-instruction 512-bit Add-with-Carry
79 may be performed by setting VL=8, and a one-instruction
80 1024-bit Add-with-Carry by setting VL=16, and so on. More on
81 this in [[openpower/sv/biginteger]]
83 # v3.0B/v3.1 relevant instructions
85 SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
88 Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
89 the sole exceptions potentially being any operations with 128-bit
90 operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar
92 SV effectively *replaces* the majority of VSX, requiring far less
93 instructions, and provides, at the very minimum, predication
94 (which VSX was designed without).
96 Likewise, Load/Store Multiple make no sense to
97 have because they are not only provided by SV, the SV alternatives may
98 be predicated as well, making them far better suited to use in function
99 calls and context-switching.
101 Additionally, some v3.0/1 instructions simply make no sense at all in a
102 Vector context: `rfid` falls into this category,
103 as well as `sc` and `scv`. Here there is simply no point
104 trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions
105 should be called instead.
107 Fortuitously this leaves several Major Opcodes free for use by SV
108 to fit alternative future instructions. In a 3D context this means
109 Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST
110 operations, and others critical to an efficient, effective 3D GPU and
111 VPU ISA. With such instructions being included as standard in other
112 commercially-successful GPU ISAs it is likewise critical that a 3D
113 GPU/VPU based on svp64 also have such instructions.
115 Note however that svp64 is stand-alone and is in no way
116 critically dependent on the existence or provision of 3D GPU or VPU
117 instructions. These should be considered entirely separate
118 extensions, and their discussion
119 and specification is out of scope for this document.
121 ## Major opcode map (v3.0B)
123 This table is taken from v3.0B.
124 Table 9: Primary Opcode Map (opcode bits 0:5)
127 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
128 000 | | | tdi | twi | EXT04 | | | mulli | 000
129 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
130 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010
131 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
132 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
133 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101
134 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
135 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
136 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
139 It is important to note that having a different v3.0B Scalar opcode
140 that is different from an SVP64 one is highly undesirable: the complexity
141 in the decoder is greatly increased, through breaking of the RISC paradigm.
143 # EXTRA Field Mapping
145 The purpose of the 9-bit EXTRA field mapping is to mark individual
146 registers (RT, RA, BFA) as either scalar or vector, and to extend
147 their numbering from 0..31 in Power ISA v3.0 to 0..127 in SVP64.
148 Three of the 9 bits may also be used up for a 2nd Predicate (Twin
149 Predication) leaving a mere 6 bits for qualifying registers. As can
150 be seen there is significant pressure on these (and in fact all) SVP64 bits.
152 In Power ISA v3.1 prefixing there are bits which describe and classify
153 the prefix in a fashion that is independent of the suffix. MLSS for
154 example. For SVP64 there is insufficient space to make the SVP64 Prefix
155 "self-describing", and consequently every single Scalar instruction
156 had to be individually analysed, by rote, to craft an EXTRA Field Mapping.
157 This process was semi-automated and is described in this section.
158 The final results, which are part of the SVP64 Specification, are here:
159 [[openpower/opcode_regs_deduped]]
161 * Firstly, every instruction's mnemonic (`add RT, RA, RB`) was analysed
162 from reading the markdown formatted version of the Scalar pseudocode
163 which is machine-readable and found in [[openpower/isatables]]. The
164 analysis gives, by instruction, a "Register Profile". `add RT, RA, RB`
165 for example is given a designation `RM-2R-1W` because it requires
166 two GPR reads and one GPR write.
167 * Secondly, the total number of registers was added up (2R-1W is 3 registers)
168 and if less than or equal to three then that instruction could be given an
169 EXTRA3 designation. Four or more is given an EXTRA2 designation because
170 there are only 9 bits available.
171 * Thirdly, the instruction was analysed to see if Twin or Single
172 Predication was suitable. As a general rule this was if there
173 was only a single operand and a single result (`extw` and LD/ST)
174 however it was found that some 2 or 3 operand instructions also
175 qualify. Given that 3 of the 9 bits of EXTRA had to be sacrificed for use
176 in Twin Predication, some compromises were made, here. LDST is
177 Twin but also has 3 operands in some operations, so only EXTRA2 can be used.
178 * Fourthly, a packing format was decided: for 2R-1W an EXTRA3 indexing
179 could have been decided
180 that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5)
181 and RT indexed 2 (EXTRA bits 6-8). In some cases (LD/ST with update)
182 RA-as-a-source is given a **different** EXTRA index from RA-as-a-result
183 (because it is possible to do, and perceived to be useful). Rc=1
184 co-results (CR0, CR1) are always given the same EXTRA index as their
185 main result (RT, FRT).
186 * Fifthly, in an automated process the results of the analysis
187 were outputted in CSV Format for use in machine-readable form
188 by sv_analysis.py <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
190 This process was laborious but logical, and, crucially, once a
191 decision is made (and ratified) cannot be reversed.
192 Qualifying future Power ISA Scalar instructions for SVP64
193 is **strongly** advised to utilise this same process and the same
194 sv_analysis.py program as a canonical method of maintaining the
195 relationships. Alterations to that same program which
196 change the Designation is **prohibited** once finalised (ratified
197 through the Power ISA WG Process). It would
198 be similar to deciding that `add` should be changed from X-Form
201 # Single Predication <a name="1p"> </a>
203 This is a standard mode normally found in Vector ISAs. every element in every source Vector and in the destination uses the same bit of one single predicate mask.
205 In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep, but depending on whether sz and/or dz are set, srcstep and
206 dststep can still potentially become different indices. Only when sz=dz
207 is srcstep guaranteed to equal dststep at all times.
209 Note that in some Mode Formats there is only one flag (zz). This indicates
210 that *both* sz *and* dz are set to the same.
218 The following schedule for srcstep and dststep will occur:
220 | srcstep | dststep | comment |
221 | ---- | ----- | -------- |
222 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
223 | 1 | 2 | sz=1 but dz=0: dst skips mask[1], src soes not |
224 | 2 | 3 | mask[src=2] and mask[dst=3] are 1 |
225 | end | end | loop has ended because dst reached VL-1 |
233 The following schedule for srcstep and dststep will occur:
235 | srcstep | dststep | comment |
236 | ---- | ----- | -------- |
237 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
238 | 2 | 1 | sz=0 but dz=1: src skips mask[1], dst does not |
239 | 3 | 2 | mask[src=3] and mask[dst=2] are 1 |
240 | end | end | loop has ended because src reached VL-1 |
242 In both these examples it is crucial to note that despite there being
243 a single predicate mask, with sz and dz being different, srcstep and
244 dststep are being requested to react differently.
252 The following schedule for srcstep and dststep will occur:
254 | srcstep | dststep | comment |
255 | ---- | ----- | -------- |
256 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
257 | 2 | 2 | sz=0 and dz=0: both src and dst skip mask[1] |
258 | 3 | 3 | mask[src=3] and mask[dst=3] are 1 |
259 | end | end | loop has ended because src and dst reached VL-1 |
261 Here, both srcstep and dststep remain in lockstep because sz=dz=1
263 # Twin Predication <a name="2p"> </a>
265 This is a novel concept that allows predication to be applied to a single
266 source and a single dest register. The following types of traditional
267 Vector operations may be encoded with it, *without requiring explicit
270 * VSPLAT (a single scalar distributed across a vector)
271 * VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
272 * VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
273 * VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
274 * VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
276 Those patterns (and more) may be applied to:
278 * mv (the usual way that V\* ISA operations are created)
279 * exts\* sign-extension
280 * rwlinm and other RS-RA shift operations (**note**: excluding
281 those that take RA as both a src and dest. These are not
282 1-src 1-dest, they are 2-src, 1-dest)
283 * LD and ST (treating AGEN as one source)
284 * FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
285 * Condition Register ops mfcr, mtcr and other similar
287 This is a huge list that creates extremely powerful combinations,
288 particularly given that one of the predicate options is `(1<<r3)`
290 Additional unusual capabilities of Twin Predication include a back-to-back
291 version of VCOMPRESS-VEXPAND which is effectively the ability to do
292 sequentially ordered multiple VINSERTs. The source predicate selects a
293 sequentially ordered subset of elements to be inserted; the destination
294 predicate specifies the sequentially ordered recipient locations.
295 This is equivalent to
296 `llvm.masked.compressstore.*`
298 `llvm.masked.expandload.*`
299 with a single instruction.
301 This extreme power and flexibility comes down to the fact that SVP64
302 is not actually a Vector ISA: it is a loop-abstraction-concept that
303 is applied *in general* to Scalar operations, just like the x86
304 `REP` instruction (if put on steroids).
306 # EXTRA Pack/Unpack Modes
308 The pack/unpack concept of VSX `vpack` is abstracted out as a Sub-Vector
309 reordering Schedule, named `RM-2P-1S1D-PU`.
310 The usual RM-2P-1S1D is reduced from EXTRA3 to EXTRA2, making
311 room for 2 extra bits that enable either "packing" or "unpacking"
312 on the subvectors vec2/3/4.
315 "normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides):
319 for j in range(SUBVL):
325 For pack/unpack (again, no elwidth overrides):
327 # yield an outer-SUBVL or inner VL loop with SUBVL
330 for j in range(SUBVL):
335 for j in range(SUBVL):
338 # walk through both source and dest indices simultaneously
339 for src_idx, dst_idx in zip(index_p(PACK), index_p(UNPACK)):
340 move_operation(RT+dst_idx, RA+src_idx)
342 "yield" from python is used here for simplicity and clarity.
343 The two Finite State Machines for the generation of the source
344 and destination element offsets progress incrementally in
347 Setting of both `PACK_en` and `UNPACK_en` is neither prohibited nor
348 `UNDEFINED` because the reordering is fully deterministic, and
349 additional REMAP reordering may be applied. For Matrix this would
350 give potentially up to 4 Dimensions of reordering.
352 Pack/Unpack applies to mv operations, mv.swizzle,
353 and some other single-source
354 single-destination operations such as Indexed LD/ST and extsw.
355 [[sv/mv.swizzle]] has a slightly different pseudocode algorithm
356 for Vertical-First Mode.
360 Reduction in SVP64 is deterministic and somewhat of a misnomer. A normal
361 Vector ISA would have explicit Reduce opcodes with defined characteristics
362 per operation: in SX Aurora there is even an additional scalar argument
363 containing the initial reduction value, and the default is either 0
364 or 1 depending on the specifics of the explicit opcode.
365 SVP64 fundamentally has to
366 utilise *existing* Scalar Power ISA v3.0B operations, which presents some
369 The solution turns out to be to simply define reduction as permitting
370 deterministic element-based schedules to be issued using the base Scalar
371 operations, and to rely on the underlying microarchitecture to resolve
372 Register Hazards at the element level. This goes back to
373 the fundamental principle that SV is nothing more than a Sub-Program-Counter
374 sitting between Decode and Issue phases.
376 For Scalar Reduction,
377 Microarchitectures *may* take opportunities to parallelise the reduction
378 but only if in doing so they preserve strict Program Order at the Element Level.
379 Opportunities where this is possible include an `OR` operation
380 or a MIN/MAX operation: it may be possible to parallelise the reduction,
381 but for Floating Point it is not permitted due to different results
382 being obtained if the reduction is not executed in strict Program-Sequential
385 In essence it becomes the programmer's responsibility to leverage the
386 pre-determined schedules to desired effect.
388 ## Scalar result reduction and iteration
390 Scalar Reduction per se does not exist, instead is implemented in SVP64
391 as a simple and natural relaxation of the usual restriction on the Vector
392 Looping which would terminate if the destination was marked as a Scalar.
393 Scalar Reduction by contrast *keeps issuing Vector Element Operations*
394 even though the destination register is marked as scalar.
395 Thus it is up to the programmer to be aware of this, observe some
396 conventions, and thus end up achieving the desired outcome of scalar
399 It is also important to appreciate that there is no
400 actual imposition or restriction on how this mode is utilised: there
401 will therefore be several valuable uses (including Vector Iteration
403 and it is up to the programmer to make best use of the
404 (strictly deterministic) capability
407 In this mode, which is suited to operations involving carry or overflow,
408 one register must be assigned, by convention by the programmer to be the
409 "accumulator". Scalar reduction is thus categorised by:
411 * One of the sources is a Vector
412 * the destination is a scalar
413 * optionally but most usefully when one source scalar register is
414 also the scalar destination (which may be informally termed
416 * That the source register type is the same as the destination register
417 type identified as the "accumulator". Scalar reduction on `cmp`,
418 `setb` or `isel` makes no sense for example because of the mixture
419 between CRs and GPRs.
421 *Note that issuing instructions in Scalar reduce mode such as `setb`
422 are neither `UNDEFINED` nor prohibited, despite them not making much
423 sense at first glance.
424 Scalar reduce is strictly defined behaviour, and the cost in
425 hardware terms of prohibition of seemingly non-sensical operations is too great.
426 Therefore it is permitted and required to be executed successfully.
427 Implementors **MAY** choose to optimise such instructions in instances
428 where their use results in "extraneous execution", i.e. where it is clear
429 that the sequence of operations, comprising multiple overwrites to
430 a scalar destination **without** cumulative, iterative, or reductive
431 behaviour (no "accumulator"), may discard all but the last element
432 operation. Identification
433 of such is trivial to do for `setb` and `cmp`: the source register type is
434 a completely different register file from the destination.
435 Likewise Scalar reduction when the destination is a Vector
436 is as if the Reduction Mode was not requested. However it would clearly
437 be unacceptable to perform such optimisations on cache-inhibited LD/ST,
438 so some considerable care needs to be taken.*
440 Typical applications include simple operations such as `ADD r3, r10.v,
441 r3` where, clearly, r3 is being used to accumulate the addition of all
442 elements of the vector starting at r10.
444 # add RT, RA,RB but when RT==RA
446 iregs[RA] += iregs[RB+i] # RT==RA
448 However, *unless* the operation is marked as "mapreduce" (`sv.add/mr`)
450 **terminates** at the first scalar operation. Only by marking the
451 operation as "mapreduce" will it continue to issue multiple sub-looped
452 (element) instructions in `Program Order`.
454 To perform the loop in reverse order, the ```RG``` (reverse gear) bit must be set. This may be useful in situations where the results may be different
455 (floating-point) if executed in a different order. Given that there is
456 no actual prohibition on Reduce Mode being applied when the destination
457 is a Vector, the "Reverse Gear" bit turns out to be a way to apply Iterative
458 or Cumulative Vector operations in reverse. `sv.add/rg r3.v, r4.v, r4.v`
459 for example will start at the opposite end of the Vector and push
460 a cumulative series of overlapping add operations into the Execution units of
461 the underlying hardware.
463 Other examples include shift-mask operations where a Vector of inserts
464 into a single destination register is required (see [[sv/bitmanip]], bmset),
465 as a way to construct
466 a value quickly from multiple arbitrary bit-ranges and bit-offsets.
467 Using the same register as both the source and destination, with Vectors
468 of different offsets masks and values to be inserted has multiple
469 applications including Video, cryptography and JIT compilation.
472 # * Vector of shift-offsets contained in RC (r12.v)
473 # * Vector of masks contained in RB (r8.v)
474 # * Vector of values to be masked-in in RA (r4.v)
475 # * Scalar destination RT (r0) to receive all mask-offset values
476 sv.bmset/mr r0, r4.v, r8.v, r12.v
478 Due to the Deterministic Scheduling,
479 Subtract and Divide are still permitted to be executed in this mode,
480 although from an algorithmic perspective it is strongly discouraged.
481 It would be better to use addition followed by one final subtract,
482 or in the case of divide, to get better accuracy, to perform a multiply
483 cascade followed by a final divide.
485 Note that single-operand or three-operand scalar-dest reduce is perfectly
486 well permitted: the programmer may still declare one register, used as
487 both a Vector source and Scalar destination, to be utilised as
488 the "accumulator". In the case of `sv.fmadds` and `sv.maddhw` etc
489 this naturally fits well with the normal expected usage of these
492 If an interrupt or exception occurs in the middle of the scalar mapreduce,
493 the scalar destination register **MUST** be updated with the current
494 (intermediate) result, because this is how ```Program Order``` is
495 preserved (Vector Loops are to be considered to be just another way of issuing instructions
496 in Program Order). In this way, after return from interrupt,
497 the scalar mapreduce may continue where it left off. This provides
498 "precise" exception behaviour.
500 Note that hardware is perfectly permitted to perform multi-issue
501 parallel optimisation of the scalar reduce operation: it's just that
502 as far as the user is concerned, all exceptions and interrupts **MUST**
505 ## Vector result reduce mode
507 Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
508 (Power ISA v3.0B) operation is leveraged, unmodified, to give the
509 *appearance* and *effect* of Reduction.
511 In Horizontal-First Mode, Vector-result reduction **requires**
512 the destination to be a Vector, which will be used to store
513 intermediary results.
515 Given that the tree-reduction schedule is deterministic,
516 Interrupts and exceptions
517 can therefore also be precise. The final result will be in the first
518 non-predicate-masked-out destination element, but due again to
519 the deterministic schedule programmers may find uses for the intermediate
522 When Rc=1 a corresponding Vector of co-resultant CRs is also
523 created. No special action is taken: the result and its CR Field
524 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
526 Note that the Schedule only makes sense on top of certain instructions:
527 X-Form with a Register Profile of `RT,RA,RB` is fine. Like Scalar
528 Reduction, nothing is prohibited:
529 the results of execution on an unsuitable instruction may simply
530 not make sense. Many 3-input instructions (madd, fmadd) unlike Scalar
531 Reduction in particular do not make sense, but `ternlogi`, if used
534 **Parallel-Reduction with Predication**
536 To avoid breaking the strict RISC-paradigm, keeping the Issue-Schedule
537 completely separate from the actual element-level (scalar) operations,
538 Move operations are **not** included in the Schedule. This means that
539 the Schedule leaves the final (scalar) result in the first-non-masked
540 element of the Vector used. With the predicate mask being dynamic
541 (but deterministic) this result could be anywhere.
543 If that result is needed to be moved to a (single) scalar register
544 then a follow-up `sv.mv/sm=predicate rt, ra.v` instruction will be
545 needed to get it, where the predicate is the exact same predicate used
546 in the prior Parallel-Reduction instruction. For *some* implementations
547 this may be a slow operation. It may be better to perform a pre-copy
548 of the values, compressing them (VREDUCE-style) into a contiguous block,
549 which will guarantee that the result goes into the very first element
550 of the destination vector.
554 The simplest usage is to perform an overwrite, specifying all three
555 register operands the same.
558 sv.add/vr 8.v, 8.v, 8.v
560 The Reduction Schedule will issue the Parallel Tree Reduction spanning
561 registers 8 through 13, by adjusting the offsets to RT, RA and RB as
562 necessary (see "Parallel Reduction algorithm" in a later section).
564 A non-overwrite is possible as well but just as with the overwrite
565 version, only those destination elements necessary for storing
566 intermediary computations will be written to: the remaining elements
567 will **not** be overwritten and will **not** be zero'd.
570 sv.add/vr 0.v, 8.v, 8.v
572 ## Sub-Vector Horizontal Reduction
574 Note that when SVM is clear and SUBVL!=1 the sub-elements are
575 *independent*, i.e. they are mapreduced per *sub-element* as a result.
576 illustration with a vec2, assuming RA==RT, e.g `sv.add/mr/vec2 r4, r4, r16.v`
578 for i in range(0, VL):
579 # RA==RT in the instruction. does not have to be
580 iregs[RT].x = op(iregs[RT].x, iregs[RB+i].x)
581 iregs[RT].y = op(iregs[RT].y, iregs[RB+i].y)
583 Thus logically there is nothing special or unanticipated about
584 `SVM=0`: it is expected behaviour according to standard SVP64
587 By contrast, when SVM is set and SUBVL!=1, a Horizontal
588 Subvector mode is enabled, which behaves very much more
589 like a traditional Vector Processor Reduction instruction.
594 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
599 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
600 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].z)
605 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
606 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].z)
607 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].w)
609 In this mode, when Rc=1 the Vector of CRs is as normal: each result
610 element creates a corresponding CR element (for the final, reduced, result).
614 1. that the destination (RT) is inherently used as an "Accumulator"
615 register, and consequently the Sub-Vector Loop is interruptible.
616 If RT is a Scalar then as usual the main VL Loop terminates at the
617 first predicated element (or the first element if unpredicated).
618 2. that the Sub-Vector designation applies to RA and RB *but not RT*.
619 3. that the number of operations executed is one less than the Sub-vector
624 Data-dependent fail-on-first has two distinct variants: one for LD/ST
626 the other for arithmetic operations (actually, CR-driven)
627 ([[sv/normal]]) and CR operations ([[sv/cr_ops]]).
629 case the assumption is that vector elements are required appear to be
630 executed in sequential Program Order, element 0 being the first.
632 * LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
633 ordinary one. Exceptions occur "as normal". However for elements 1
634 and above, if an exception would occur, then VL is **truncated** to the
636 * Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
637 CR-creating operation produces a result (including cmp). Similar to
638 branch, an analysis of the CR is performed and if the test fails, the
639 vector operation terminates and discards all element operations
640 above the current one (and the current one if VLi is not set),
641 and VL is truncated to either
642 the *previous* element or the current one, depending on whether
643 VLi (VL "inclusive") is set.
645 Thus the new VL comprises a contiguous vector of results,
646 all of which pass the testing criteria (equal to zero, less than zero).
648 The CR-based data-driven fail-on-first is new and not found in ARM
649 SVE or RVV. It is extremely useful for reducing instruction count,
650 however requires speculative execution involving modifications of VL
651 to get high performance implementations. An additional mode (RC1=1)
652 effectively turns what would otherwise be an arithmetic operation
653 into a type of `cmp`. The CR is stored (and the CR.eq bit tested
654 against the `inv` field).
655 If the CR.eq bit is equal to `inv` then the Vector is truncated and
657 Note that when RC1=1 the result elements are never stored, only the CRs.
659 VLi is only available as an option when `Rc=0` (or for instructions
660 which do not have Rc). When set, the current element is always
661 also included in the count (the new length that VL will be set to).
662 This may be useful in combination with "inv" to truncate the Vector
663 to *exclude* elements that fail a test, or, in the case of implementations
664 of strncpy, to include the terminating zero.
666 In CR-based data-driven fail-on-first there is only the option to select
667 and test one bit of each CR (just as with branch BO). For more complex
668 tests this may be insufficient. If that is the case, a vectorised crops
669 (crand, cror) may be used, and ffirst applied to the crop instead of to
670 the arithmetic vector.
672 One extremely important aspect of ffirst is:
674 * LDST ffirst may never set VL equal to zero. This because on the first
675 element an exception must be raised "as normal".
676 * CR-based data-dependent ffirst on the other hand **can** set VL equal
677 to zero. This is the only means in the entirety of SV that VL may be set
678 to zero (with the exception of via the SV.STATE SPR). When VL is set
679 zero due to the first element failing the CR bit-test, all subsequent
680 vectorised operations are effectively `nops` which is
681 *precisely the desired and intended behaviour*.
683 Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily
684 to a nonzero value for any implementation-specific reason. For example:
685 it is perfectly reasonable for implementations to alter VL when ffirst
686 LD or ST operations are initiated on a nonaligned boundary, such that
687 within a loop the subsequent iteration of that loop begins subsequent
688 ffirst LD/ST operations on an aligned boundary. Likewise, to reduce
689 workloads or balance resources.
691 CR-based data-dependent first on the other hand MUST not truncate VL
692 arbitrarily to a length decided by the hardware: VL MUST only be
693 truncated based explicitly on whether a test fails.
694 This because it is a precise test on which algorithms
697 ## Data-dependent fail-first on CR operations (crand etc)
699 Operations that actually produce or alter CR Field as a result
700 do not also in turn have an Rc=1 mode. However it makes no
701 sense to try to test the 4 bits of a CR Field for being equal
702 or not equal to zero. Moreover, the result is already in the
703 form that is desired: it is a CR field. Therefore,
704 CR-based operations have their own SVP64 Mode, described
707 There are two primary different types of CR operations:
709 * Those which have a 3-bit operand field (referring to a CR Field)
710 * Those which have a 5-bit operand (referring to a bit within the
713 More details can be found in [[sv/cr_ops]].
717 Pred-result mode may not be applied on CR-based operations.
719 Although CR operations (mtcr, crand, cror) may be Vectorised,
720 predicated, pred-result mode applies to operations that have
721 an Rc=1 mode, or make sense to add an RC1 option.
723 Predicate-result merges common CR testing with predication, saving on
724 instruction count. In essence, a Condition Register Field test
725 is performed, and if it fails it is considered to have been
726 *as if* the destination predicate bit was zero. Given that
727 there are no CR-based operations that produce Rc=1 co-results,
728 there can be no pred-result mode for mtcr and other CR-based instructions
730 Arithmetic and Logical Pred-result, which does have Rc=1 or for which
731 RC1 Mode makes sense, is covered in [[sv/normal]]
735 CRs are slightly more involved than INT or FP registers due to the
736 possibility for indexing individual bits (crops BA/BB/BT). Again however
737 the access pattern needs to be understandable in relation to v3.0B / v3.1B
738 numbering, with a clear linear relationship and mapping existing when
741 ## CR EXTRA mapping table and algorithm <a name="cr_extra"></a>
743 Numbering relationships for CR fields are already complex due to being
744 in BE format (*the relationship is not clearly explained in the v3.0B
745 or v3.1 specification*). However with some care and consideration
746 the exact same mapping used for INT and FP regfiles may be applied,
747 just to the upper bits, as explained below. The notation
748 `CR{field number}` is used to indicate access to a particular
749 Condition Register Field (as opposed to the notation `CR[bit]`
750 which accesses one bit of the 32 bit Power ISA v3.0B
753 `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is defined, in v3.0B pseudocode, as:
755 CR{7-n} = CR[32+n*4:35+n*4]
757 For SVP64 the relationship for the sequential
758 numbering of elements is to the CR **fields** within
759 the CR Register, not to individual bits within the CR register.
761 In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (0:2)
762 select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
763 *in* that CR (EQ/LT/GT/SO). The numbering was determined (after 4 months of
764 analysis and research) to be as follows:
766 CR_index = 7-(BA>>2) # top 3 bits but BE
767 bit_index = 3-(BA & 0b11) # low 2 bits but BE
768 CR_reg = CR{CR_index} # get the CR
769 # finally get the bit from the CR.
770 CR_bit = (CR_reg & (1<<bit_index)) != 0
772 When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
773 applies, **not** the CR\_bit portion (bits 3-4):
778 spec = EXTRA2<<1 | 0b0
780 # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
781 return ((BA >> 2)<<6) | # hi 3 bits shifted up
782 (spec[1:2]<<4) | # to make room for these
783 (BA & 0b11) # CR_bit on the end
785 # scalar constructs "00 spec[1:2] BA[0:4]"
786 return (spec[1:2] << 5) | BA
788 Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
789 algorithm to determine CR\_reg is modified to as follows:
791 CR_index = 7-(BA>>2) # top 3 bits but BE
793 # vector mode, 0-124 increments of 4
794 CR_index = (CR_index<<4) | (spec[1:2] << 2)
796 # scalar mode, 0-32 increments of 1
797 CR_index = (spec[1:2]<<3) | CR_index
798 # same as for v3.0/v3.1 from this point onwards
799 bit_index = 3-(BA & 0b11) # low 2 bits but BE
800 CR_reg = CR{CR_index} # get the CR
801 # finally get the bit from the CR.
802 CR_bit = (CR_reg & (1<<bit_index)) != 0
804 Note here that the decoding pattern to determine CR\_bit does not change.
806 Note: high-performance implementations may read/write Vectors of CRs in
807 batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
808 simplify internal design. If instructions are issued where CR Vectors
809 do not start on a 32-bit aligned boundary, performance may be affected.
811 ## CR fields as inputs/outputs of vector operations
813 CRs (or, the arithmetic operations associated with them)
814 may be marked as Vectorised or Scalar. When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised. Likewise if the destination is scalar then so is the CR.
816 When vectorized, the CR inputs/outputs are sequentially read/written
817 to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin
818 writing to CR8 (TBD evaluate) and increase sequentially from there.
821 * implementations may rely on the Vector CRs being aligned to 8. This
822 means that CRs may be read or written in aligned batches of 32 bits
823 (8 CRs per batch), for high performance implementations.
824 * scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
825 overwritten by vector Rc=1 operations except for very large VL
826 * CR-based predication, from CR32, is also not interfered with
827 (except by large VL).
829 However when the SV result (destination) is marked as a scalar by the
830 EXTRA field the *standard* v3.0B behaviour applies: the accompanying
831 CR when Rc=1 is written to. This is CR0 for integer operations and CR1
834 Note that yes, the CR Fields are genuinely Vectorised. Unlike in SIMD VSX which
835 has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
836 v3.0B scalar operations produce a **tuple** of element results: the
837 result of the operation as one part of that element *and a corresponding
838 CR element*. Greatly simplified pseudocode:
841 # calculate the vector result of an add
842 iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
843 # now calculate CR bits
844 CRs{8+i}.eq = iregs[RT+i] == 0
845 CRs{8+i}.gt = iregs[RT+i] > 0
848 If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
849 then a followup instruction must be performed, setting "reduce" mode on
850 the Vector of CRs, using cr ops (crand, crnor) to do so. This provides far
851 more flexibility in analysing vectors than standard Vector ISAs. Normal
852 Vector ISAs are typically restricted to "were all results nonzero" and
853 "were some results nonzero". The application of mapreduce to Vectorised
854 cr operations allows far more sophisticated analysis, particularly in
855 conjunction with the new crweird operations see [[sv/cr_int_predication]].
857 Note in particular that the use of a separate instruction in this way
858 ensures that high performance multi-issue OoO inplementations do not
859 have the computation of the cumulative analysis CR as a bottleneck and
860 hindrance, regardless of the length of VL.
863 SVP64 [[sv/branches]] may be used, even when the branch itself is to
864 the following instruction. The combined side-effects of CTR reduction
865 and VL truncation provide several benefits.
867 (see [[discussion]]. some alternative schemes are described there)
869 ## Rc=1 when SUBVL!=1
871 sub-vectors are effectively a form of Packed SIMD (length 2 to 4). Only 1 bit of
872 predicate is allocated per subvector; likewise only one CR is allocated
875 This leaves a conundrum as to how to apply CR computation per subvector,
876 when normally Rc=1 is exclusively applied to scalar elements. A solution
877 is to perform a bitwise OR or AND of the subvector tests. Given that
878 OE is ignored in SVP64, this field may (when available) be used to select OR or
881 ### Table of CR fields
883 CRn is the notation used by the OpenPower spec to refer to CR field #i,
884 so FP instructions with Rc=1 write to CR1 (n=1).
886 CRs are not stored in SPRs: they are registers in their own right.
887 Therefore context-switching the full set of CRs involves a Vectorised
888 mfcr or mtcr, using VL=8 to do so. This is exactly as how
889 scalar OpenPOWER context-switches CRs: it is just that there are now
892 The 64 SV CRs are arranged similarly to the way the 128 integer registers
893 are arranged. TODO a python program that auto-generates a CSV file
894 which can be included in a table, which is in a new page (so as not to
895 overwhelm this one). [[svp64/cr_names]]
899 Instructions are broken down by Register Profiles as listed in the
900 following auto-generated page: [[opcode_regs_deduped]]. These tables,
901 despite being auto-generated, are part of the Specification.
903 # SV pseudocode illilustration
905 ## Single-predicated Instruction
907 illustration of normal mode add operation: zeroing not included, elwidth
908 overrides not included. if there is no predicate, it is set to all 1s
910 function op_add(rd, rs1, rs2) # add not VADD!
911 int i, id=0, irs1=0, irs2=0;
912 predval = get_pred_val(FALSE, rd);
913 for (i = 0; i < VL; i++)
914 STATE.srcoffs = i # save context
915 if (predval & 1<<i) # predication uses intregs
916 ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
917 if (!int_vec[rd].isvec) break;
918 if (rd.isvec) { id += 1; }
919 if (rs1.isvec) { irs1 += 1; }
920 if (rs2.isvec) { irs2 += 1; }
921 if (id == VL or irs1 == VL or irs2 == VL)
923 # end VL hardware loop
924 STATE.srcoffs = 0; # reset
928 This has several modes:
931 * RT.v = RA.v RB.s (and RA.s RB.v)
934 * RT.s = RA.v RB.s (and RA.s RB.v)
937 All of these may be predicated. Vector-Vector is straightfoward.
938 When one of source is a Vector and the other a Scalar, it is clear that
939 each element of the Vector source should be added to the Scalar source,
940 each result placed into the Vector (or, if the destination is a scalar,
941 only the first nonpredicated result).
943 The one that is not obvious is RT=vector but both RA/RB=scalar.
944 Here this acts as a "splat scalar result", copying the same result into
945 all nonpredicated result elements. If a fixed destination scalar was
946 intended, then an all-Scalar operation should be used.
948 See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
950 # Assembly Annotation
952 Assembly code annotation is required for SV to be able to successfully
953 mark instructions as "prefixed".
955 A reasonable (prototype) starting point:
961 * ew=8/16/32 - element width
962 * sew=8/16/32 - source element width
964 * mode=mr/satu/sats/crpred
965 * pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
967 similar to x86 "rex" prefix.
969 For actual assembler:
971 sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
975 * m={pred}: predicate mask mode
976 * sm={pred}: source-predicate mask mode (only allowed in Twin-predication)
977 * vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
978 * ew={N}: ew=8/16/32 - sets elwidth override
979 * sw={N}: sw=8/16/32 - sets source elwidth override
980 * ff={xx}: see fail-first mode
981 * pr={xx}: see predicate-result mode
982 * sat{x}: satu / sats - see saturation mode
983 * mr: see map-reduce mode
984 * mr.svm see map-reduce with sub-vector mode
985 * crm: see map-reduce CR mode
986 * crm.svm see map-reduce CR with sub-vector mode
987 * sz: predication with source-zeroing
988 * dz: predication with dest-zeroing
993 - pm=lt/gt/le/ge/eq/ne/so/ns
996 - ff=lt/gt/le/ge/eq/ne/so/ns
1002 - mr OR crm: "normal" map-reduce mode or CR-mode.
1003 - mr.svm OR crm.svm: when vec2/3/4 set, sub-vector mapreduce is enabled
1005 # Parallel-reduction algorithm
1007 The principle of SVP64 is that SVP64 is a fully-independent
1008 Abstraction of hardware-looping in between issue and execute phases
1009 that has no relation to the operation it issues.
1010 Additional state cannot be saved on context-switching beyond that
1011 of SVSTATE, making things slightly tricky.
1013 Executable demo pseudocode, full version
1014 [here](https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_preduce.py;hb=HEAD)
1017 [[!inline raw="yes" pages="openpower/sv/preduce.py" ]]
1020 This algorithm works by noting when data remains in-place rather than
1021 being reduced, and referring to that alternative position on subsequent
1022 layers of reduction. It is re-entrant. If however interrupted and
1023 restored, some implementations may take longer to re-establish the
1026 Its application by default is that:
1028 * RA, FRA or BFA is the first register as the first operand
1029 (ci index offset in the above pseudocode)
1030 * RB, FRB or BFB is the second (co index offset)
1031 * RT (result) also uses ci **if RA==RT**
1033 For more complex applications a REMAP Schedule must be used
1035 *Programmers's note:
1036 if passed a predicate mask with only one bit set, this algorithm
1037 takes no action, similar to when a predicate mask is all zero.*
1039 *Implementor's Note: many SIMD-based Parallel Reduction Algorithms are
1040 implemented in hardware with MVs that ensure lane-crossing is minimised.
1041 The mistake which would be catastrophic to SVP64 to make is to then
1042 limit the Reduction Sequence for all implementors
1043 based solely and exclusively on what one
1044 specific internal microarchitecture does.
1045 In SIMD ISAs the internal SIMD Architectural design is exposed and imposed on the programmer. Cray-style Vector ISAs on the other hand provide convenient,
1046 compact and efficient encodings of abstract concepts.*
1047 **It is the Implementor's responsibility to produce a design
1048 that complies with the above algorithm,
1049 utilising internal Micro-coding and other techniques to transparently
1050 insert micro-architectural lane-crossing Move operations
1051 if necessary or desired, to give the level of efficiency or performance
1054 # Element-width overrides <a name="elwidth"> </>
1056 Element-width overrides are best illustrated with a packed structure
1057 union in the c programming language. The following should be taken
1058 literally, and assume always a little-endian layout:
1065 uint8_t actual_bytes[8];
1068 elreg_t int_regfile[128];
1070 get_polymorphed_reg(reg, bitwidth, offset):
1072 res.l = 0; // TODO: going to need sign-extending / zero-extending
1074 reg.b = int_regfile[reg].b[offset]
1075 elif bitwidth == 16:
1076 reg.s = int_regfile[reg].s[offset]
1077 elif bitwidth == 32:
1078 reg.i = int_regfile[reg].i[offset]
1079 elif bitwidth == 64:
1080 reg.l = int_regfile[reg].l[offset]
1083 set_polymorphed_reg(reg, bitwidth, offset, val):
1085 # not a vector: first element only, overwrites high bits
1086 int_regfile[reg].l[0] = val
1088 int_regfile[reg].b[offset] = val
1089 elif bitwidth == 16:
1090 int_regfile[reg].s[offset] = val
1091 elif bitwidth == 32:
1092 int_regfile[reg].i[offset] = val
1093 elif bitwidth == 64:
1094 int_regfile[reg].l[offset] = val
1096 In effect the GPR registers r0 to r127 (and corresponding FPRs fp0
1097 to fp127) are reinterpreted to be "starting points" in a byte-addressable
1098 memory. Vectors - which become just a virtual naming construct - effectively
1101 It is extremely important for implementors to note that the only circumstance
1102 where upper portions of an underlying 64-bit register are zero'd out is
1103 when the destination is a scalar. The ideal register file has byte-level
1104 write-enable lines, just like most SRAMs, in order to avoid READ-MODIFY-WRITE.
1106 An example ADD operation with predication and element width overrides:
1108 for (i = 0; i < VL; i++)
1109 if (predval & 1<<i) # predication
1110 src1 = get_polymorphed_reg(RA, srcwid, irs1)
1111 src2 = get_polymorphed_reg(RB, srcwid, irs2)
1112 result = src1 + src2 # actual add here
1113 set_polymorphed_reg(RT, destwid, ird, result)
1114 if (!RT.isvec) break
1115 if (RT.isvec) { id += 1; }
1116 if (RA.isvec) { irs1 += 1; }
1117 if (RB.isvec) { irs2 += 1; }
1119 Thus it can be clearly seen that elements are packed by their
1120 element width, and the packing starts from the source (or destination)
1121 specified by the instruction.
1123 # Twin (implicit) result operations
1125 Some operations in the Power ISA already target two 64-bit scalar
1126 registers: `lq` for example, and LD with update.
1127 Some mathematical algorithms are more
1128 efficient when there are two outputs rather than one, providing
1129 feedback loops between elements (the most well-known being add with
1130 carry). 64-bit multiply
1131 for example actually internally produces a 128 bit result, which clearly
1132 cannot be stored in a single 64 bit register. Some ISAs recommend
1133 "macro op fusion": the practice of setting a convention whereby if
1134 two commonly used instructions (mullo, mulhi) use the same ALU but
1135 one selects the low part of an identical operation and the other
1136 selects the high part, then optimised micro-architectures may
1137 "fuse" those two instructions together, using Micro-coding techniques,
1140 The practice and convention of macro-op fusion however is not compatible
1141 with SVP64 Horizontal-First, because Horizontal Mode may only
1142 be applied to a single instruction at a time, and SVP64 is based on
1143 the principle of strict Program Order even at the element
1144 level. Thus it becomes
1145 necessary to add explicit more complex single instructions with
1146 more operands than would normally be seen in the average RISC ISA
1147 (3-in, 2-out, in some cases). If it
1148 was not for Power ISA already having LD/ST with update as well as
1149 Condition Codes and `lq` this would be hard to justify.
1151 With limited space in the `EXTRA` Field, and Power ISA opcodes
1152 being only 32 bit, 5 operands is quite an ask. `lq` however sets
1153 a precedent: `RTp` stands for "RT pair". In other words the result
1154 is stored in RT and RT+1. For Scalar operations, following this
1155 precedent is perfectly reasonable. In Scalar mode,
1156 `madded` therefore stores the two halves of the 128-bit multiply
1159 What, then, of `sv.madded`? If the destination is hard-coded to
1160 RT and RT+1 the instruction is not useful when Vectorised because
1161 the output will be overwritten on the next element. To solve this
1162 is easy: define the destination registers as RT and RT+MAXVL
1163 respectively. This makes it easy for compilers to statically allocate
1164 registers even when VL changes dynamically.
1166 Bear in mind that both RT and RT+MAXVL are starting points for Vectors,
1167 and bear in mind that element-width overrides still have to be taken
1168 into consideration, the starting point for the implicit destination
1169 is best illustrated in pseudocode:
1172 for (i = 0; i < VL; i++)
1173 if (predval & 1<<i) # predication
1174 src1 = get_polymorphed_reg(RA, srcwid, irs1)
1175 src2 = get_polymorphed_reg(RB, srcwid, irs2)
1176 src2 = get_polymorphed_reg(RC, srcwid, irs3)
1177 result = src1*src2 + src2
1178 destmask = (2<<destwid)-1
1179 # store two halves of result, both start from RT.
1180 set_polymorphed_reg(RT, destwid, ird , result&destmask)
1181 set_polymorphed_reg(RT, destwid, ird+MAXVL, result>>destwid)
1182 if (!RT.isvec) break
1183 if (RT.isvec) { id += 1; }
1184 if (RA.isvec) { irs1 += 1; }
1185 if (RB.isvec) { irs2 += 1; }
1186 if (RC.isvec) { irs3 += 1; }
1188 The significant part here is that the second half is stored
1189 starting not from RT+MAXVL at all: it is the *element* index
1190 that is offset by MAXVL, both halves actually starting from RT.
1191 If VL is 3, MAXVL is 5, RT is 1, and dest elwidth is 32 then the elements
1192 RT0 to RT2 are stored:
1195 r0 unchanged unchanged
1200 r5 unchanged unchanged
1202 Note that all of the LO halves start from r1, but that the HI halves
1203 start from half-way into r3. The reason is that with MAXVL bring
1204 5 and elwidth being 32, this is the 5th element
1205 offset (in 32 bit quantities) counting from r1.
1207 *Programmer's note: accessing registers that have been placed
1208 starting on a non-contiguous boundary (half-way along a scalar
1209 register) can be inconvenient: REMAP can provide an offset but
1210 it requires extra instructions to set up. A simple solution
1211 is to ensure that MAXVL is rounded up such that the Vector
1212 ends cleanly on a contiguous register boundary. MAXVL=6 in
1213 the above example would achieve that*
1215 Additional DRAFT Scalar instructions in 3-in 2-out form
1216 with an implicit 2nd destination:
1218 * [[isa/svfixedarith]]