3 # DRAFT SVP64 for OpenPOWER ISA v3.0B
5 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. It is in Draft Status and
8 will be submitted to the [[!wikipedia OpenPOWER_Foundation]] ISA WG
9 via the External RFC Process.
11 Credits and acknowledgements:
19 * NLnet Foundation, for funding
20 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
27 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
28 * [[svp64/discussion]]
30 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
31 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
41 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section.
43 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
44 and counting up as you move to the LSB end). All bit ranges are inclusive
45 (so `4:6` means bits 4, 5, and 6).
47 64-bit instructions are split into two 32-bit words, the prefix and the
48 suffix. The prefix always comes before the suffix in PC order.
51 |--------|--------------|--------------|
52 | EXT01 | v3.1 Prefix | v3.1 Suffix |
54 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
56 Subset implementations in hardware are permitted, as long as certain
57 rules are followed, allowing for full soft-emulation including future
58 revisions. Details in the [[svp64/appendix]].
60 ## SVP64 encoding features
62 A number of features need to be compacted into a very small space of only 24 bits:
64 * Independent per-register Scalar/Vector tagging and range extension on every register
65 * Element width overrides on both source and destination
66 * Predication on both source and destination
67 * Two different sources of predication: INT and CR Fields
68 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
69 predicate-result mode.
71 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
73 # Definition of Reserved in this spec.
75 For the new fields added in SVP64, instructions that have any of their
76 fields set to a reserved value must cause an illegal instruction trap,
77 to allow emulation of future instruction sets, or for subsets of SVP64
78 to be implemented in hardware and the rest emulated.
79 This includes SVP64 SPRs: reading or writing values which are not
80 supported in hardware must also raise illegal instruction traps
81 in order to allow emulation.
82 Unless otherwise stated, reserved values are always all zeros.
84 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
85 is intended the red keyword `RESERVED` is used.
87 # Scalar Identity Behaviour
89 SVP64 is designed so that when the prefix is all zeros, and
91 influence occurs (no augmentation) such that all standard OpenPOWER
92 v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
94 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
95 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
97 # Register Naming and size
99 SV Registers are simply the INT, FP and CR register files extended
100 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
102 Where the integer regfile in standard scalar
103 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
104 Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields
106 extended to 128 entries, CR0 thru CR127.
108 The names of the registers therefore reflects a simple linear extension
109 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
110 would be reflected by a linear increase in the size of the underlying
111 SRAM used for the regfiles.
113 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
114 so that the register fields are identical to as if SV was not in effect
115 i.e. under these circumstances (EXTRA=0) the register field names RA,
116 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
117 `scalar identity behaviour` described above.
121 With the way that EXTRA fields are defined and applied to register fields,
122 future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Further discussion is out of scope for this version of SVP64.
124 # Remapped Encoding (`RM[0:23]`)
126 To allow relatively easy remapping of which portions of the Prefix Opcode
127 Map are used for SVP64 without needing to rewrite a large portion of the
128 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
129 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
132 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
133 is defined in the Prefix Fields section.
135 ## Prefix Opcode Map (64-bit instruction encoding)
137 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
139 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
140 empty spaces are yet-to-be-allocated Illegal Instructions.
142 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
143 |------|--------|--------|--------|--------|--------|--------|--------|--------|
144 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
145 |001---| | | | | | | | |
146 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
147 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
148 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
149 |101---| | | | | | | | |
150 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
151 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
153 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
157 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
158 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
159 This is achieved by setting bits 7 and 9 to 1:
161 | Name | Bits | Value | Description |
162 |------------|---------|-------|--------------------------------|
163 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
164 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
165 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
166 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
167 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
168 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
170 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
173 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
174 |--------|-------|---|-------|---|----------|
175 | EXT01 | RM | 1 | RM | 1 | RM |
176 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
178 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
179 instruction. That instruction becomes "prefixed" with the SVP context: the
180 Remapped Encoding field (RM).
182 It is important to note that unlike v3.1 64-bit prefixed instructions
183 there is insufficient space in `RM` to provide identification of
184 any SVP64 Fields without first partially decoding the
185 32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
186 `RM` format is individually associated with every instruction.
188 Extreme caution and care must therefore be taken
189 when extending SVP64 in future, to not create unnecessary relationships
190 between prefix and suffix that could complicate decoding, adding latency.
194 The following fields are common to all Remapped Encodings:
196 | Field Name | Field bits | Description |
197 |------------|------------|----------------------------------------|
198 | MASKMODE | `0` | Execution (predication) Mask Kind |
199 | MASK | `1:3` | Execution Mask |
200 | SUBVL | `8:9` | Sub-vector length |
202 The following fields are optional or encoded differently depending
203 on context after decoding of the Scalar suffix:
205 | Field Name | Field bits | Description |
206 |------------|------------|----------------------------------------|
207 | ELWIDTH | `4:5` | Element Width |
208 | ELWIDTH_SRC | `6:7` | Element Width for Source |
209 | EXTRA | `10:18` | Register Extra encoding |
210 | MODE | `19:23` | changes Vector behaviour |
212 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
213 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
214 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
215 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
216 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
218 Similar to OpenPOWER `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
220 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
224 Mode is an augmentation of SV behaviour. Different types of
225 instructions have different needs, similar to Power ISA
226 v3.1 64 bit prefix 8LS and MTRR formats apply to different
227 instruction types. Modes include Reduction, Iteration, arithmetic
228 saturation, and Fail-First. More specific details in each
229 section and in the [[svp64/appendix]]
231 * For condition register operations see [[sv/cr_ops]]
232 * For LD/ST Modes, see [[sv/ldst]].
233 * For Branch modes, see [[sv/branches]]
234 * For arithmetic and logical, see [[sv/normal]]
238 Default behaviour is set to 0b00 so that zeros follow the convention of
239 `scalar identity behaviour`. In this case it means that elwidth overrides
240 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
241 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
242 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
243 states that, again, the behaviour is not to be modified.
245 Only when elwidth is nonzero is the element width overridden to the
246 explicitly required value.
248 ## Elwidth for Integers:
250 | Value | Mnemonic | Description |
251 |-------|----------------|------------------------------------|
252 | 00 | DEFAULT | default behaviour for operation |
253 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
254 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
255 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
257 This encoding is chosen such that the byte width may be computed as
260 ## Elwidth for FP Registers:
262 | Value | Mnemonic | Description |
263 |-------|----------------|------------------------------------|
264 | 00 | DEFAULT | default behaviour for FP operation |
265 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
266 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
267 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
270 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
271 is reserved for a future implementation of SV
273 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
274 perform its operation at **half** the ELWIDTH then padded back out
275 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
276 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
277 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
278 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
279 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
280 (IEEE754 FP8 or BF8 are not defined).
284 Element-width overrides for CR Fields has no meaning. The bits
285 are therefore used for other purposes, or when Rc=1, the Elwidth
286 applies to the result being tested, but not to the Vector of CR Fields.
291 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
292 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
293 lines up in combination with all other "default is all zeros" behaviour.
295 | Value | Mnemonic | Subvec | Description |
296 |-------|-----------|---------|------------------------|
297 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
298 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
299 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
300 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
302 The SUBVL encoding value may be thought of as an inclusive range of a
303 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
304 this may be considered to be elements 0b00 to 0b01 inclusive.
306 # MASK/MASK_SRC & MASKMODE Encoding
308 TODO: rename MASK_KIND to MASKMODE
310 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
311 types may not be mixed.
313 Special note: to disable predication this field must
314 be set to zero in combination with Integer Predication also being set
315 to 0b000. this has the effect of enabling "all 1s" in the predicate
316 mask, which is equivalent to "not having any predication at all"
317 and consequently, in combination with all other default zeros, fully
318 disables SV (`scalar identity behaviour`).
320 `MASKMODE` may be set to one of 2 values:
322 | Value | Description |
323 |-----------|------------------------------------------------------|
324 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
325 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
327 Integer Twin predication has a second set of 3 bits that uses the same
328 encoding thus allowing either the same register (r3 or r10) to be used
329 for both src and dest, or different regs (one for src, one for dest).
331 Likewise CR based twin predication has a second set of 3 bits, allowing
332 a different test to be applied.
334 Note that it is assumed that Predicate Masks (whether INT or CR)
335 are read *before* the operations proceed. In practice (for CR Fields)
336 this creates an unnecessary block on parallelism. Therefore,
337 it is up to the programmer to ensure that the CR fields used as
338 Predicate Masks are not being written to by any parallel Vector Loop.
339 Doing so results in **UNDEFINED** behaviour, according to the definition
340 outlined in the OpenPOWER v3.0B Specification.
342 Hardware Implementations are therefore free and clear to delay reading
343 of individual CR fields until the actual predicated element operation
344 needs to take place, safe in the knowledge that no programmer will
345 have issued a Vector Instruction where previous elements could have
346 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
348 ## Integer Predication (MASKMODE=0)
350 When the predicate mode bit is zero the 3 bits are interpreted as below.
351 Twin predication has an identical 3 bit field similarly encoded.
353 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
355 | Value | Mnemonic | Element `i` enabled if: |
356 |-------|----------|------------------------------|
357 | 000 | ALWAYS | predicate effectively all 1s |
358 | 001 | 1 << R3 | `i == R3` |
359 | 010 | R3 | `R3 & (1 << i)` is non-zero |
360 | 011 | ~R3 | `R3 & (1 << i)` is zero |
361 | 100 | R10 | `R10 & (1 << i)` is non-zero |
362 | 101 | ~R10 | `R10 & (1 << i)` is zero |
363 | 110 | R30 | `R30 & (1 << i)` is non-zero |
364 | 111 | ~R30 | `R30 & (1 << i)` is zero |
366 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
368 ## CR-based Predication (MASKMODE=1)
370 When the predicate mode bit is one the 3 bits are interpreted as below.
371 Twin predication has an identical 3 bit field similarly encoded.
373 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
375 | Value | Mnemonic | Element `i` is enabled if |
376 |-------|----------|--------------------------|
377 | 000 | lt | `CR[offs+i].LT` is set |
378 | 001 | nl/ge | `CR[offs+i].LT` is clear |
379 | 010 | gt | `CR[offs+i].GT` is set |
380 | 011 | ng/le | `CR[offs+i].GT` is clear |
381 | 100 | eq | `CR[offs+i].EQ` is set |
382 | 101 | ne | `CR[offs+i].EQ` is clear |
383 | 110 | so/un | `CR[offs+i].FU` is set |
384 | 111 | ns/nu | `CR[offs+i].FU` is clear |
386 CR based predication. TODO: select alternate CR for twin predication? see
387 [[discussion]] Overlap of the two CR based predicates must be taken
388 into account, so the starting point for one of them must be suitably
389 high, or accept that for twin predication VL must not exceed the range
390 where overlap will occur, *or* that they use the same starting point
391 but select different *bits* of the same CRs
393 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
395 The CR Predicates chosen must start on a boundary that Vectorised
396 CR operations can access cleanly, in full.
397 With EXTRA2 restricting starting points
398 to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and CR Predicate
399 Masks have to be adapted to fit on these boundaries as well.
401 # Extra Remapped Encoding <a name="extra_remap"> </a>
403 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
405 These mappings are part of the SVP64 Specification in exactly the same
406 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
407 will need a corresponding SVP64 Mapping, which can be derived by-rote
408 from examining the Register "Profile" of the instruction.
410 There are two categories: Single and Twin Predication.
411 Due to space considerations further subdivision of Single Predication
412 is based on whether the number of src operands is 2 or 3. With only
413 9 bits available some compromises have to be made.
415 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
416 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
417 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
418 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
419 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
420 * `RM-2P-1S1D-PU` Twin Predication (src=1, dest=1), Pack/Unpack, primarily
425 | Field Name | Field bits | Description |
426 |------------|------------|----------------------------------------|
427 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
428 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
429 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
430 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
431 | EXTRA2_MODE | `18` | used by `divmod2du` and `madded` for RS |
433 These are for 3 operand in and either 1 or 2 out instructions.
434 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
435 such as `madded` have an implicit second destination, RS, the
436 selection of which is determined by bit 18.
440 | Field Name | Field bits | Description |
441 |------------|------------|-------------------------------------------|
442 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
443 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
444 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
446 These are for 2 operand 1 dest instructions, such as `add RT, RA,
447 RB`. However also included are unusual instructions with an implicit dest
448 that is identical to its src reg, such as `rlwinmi`.
450 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
451 an alternative destination. With SV however this becomes possible.
452 Therefore, the fact that the dest is implicitly also a src should not
453 mislead: due to the *prefix* they are different SV regs.
455 * `rlwimi RA, RS, ...`
456 * Rsrc1_EXTRA3 applies to RS as the first src
457 * Rsrc2_EXTRA3 applies to RA as the secomd src
458 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
460 With the addition of the EXTRA bits, the three registers
461 each may be *independently* made vector or scalar, and be independently
462 augmented to 7 bits in length.
466 | Field Name | Field bits | Description |
467 |------------|------------|----------------------------|
468 | Rdest_EXTRA3 | `10:12` | extends Rdest |
469 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
470 | MASK_SRC | `16:18` | Execution Mask for Source |
472 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
476 | Field Name | Field bits | Description |
477 |------------|------------|----------------------------|
478 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
479 | Rsrc_EXTRA2 | `12:13` | extends Rsrc (R\*\_EXTRA2 Encoding) |
480 | PACK_en | `14` | Enable pack |
481 | UNPACK_en | `15` | Enable unpack |
482 | MASK_SRC | `16:18` | Execution Mask for Source |
484 for [[sv/mv.vec]], [[sv/mv.swizzle]] and also LD/ST (without index)
488 single-predicate, three registers (2 read, 1 write)
490 | Field Name | Field bits | Description |
491 |------------|------------|----------------------------|
492 | Rdest_EXTRA3 | `10:12` | extends Rdest |
493 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
494 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
496 ## RM-2P-2S1D/1S2D/3S
498 The primary purpose for this encoding is for Twin Predication on LOAD
499 and STORE operations. see [[sv/ldst]] for detailed anslysis.
503 | Field Name | Field bits | Description |
504 |------------|------------|----------------------------|
505 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
506 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
507 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
508 | MASK_SRC | `16:18` | Execution Mask for Source |
510 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
511 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
513 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
515 Note also that LD with update indexed, which takes 2 src and 2 dest
516 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
517 Twin Predication. therefore these are treated as RM-2P-2S1D and the
518 src spec for RA is also used for the same RA as a dest.
520 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
524 EXTRA is the means by which two things are achieved:
526 1. Registers are marked as either Vector *or Scalar*
527 2. Register field numbers (limited typically to 5 bit)
528 are extended in range, both for Scalar and Vector.
530 The register files are therefore extended:
532 * INT is extended from r0-31 to r0-127
533 * FP is extended from fp0-32 to fp0-fp127
534 * CR Fields are extended from CR0-7 to CR0-127
536 In the following tables register numbers are constructed from the
537 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
538 or EXTRA3 field from the SV Prefix, determined by the specific
539 RM-xx-yyyy designation for a given instruction.
540 The prefixing is arranged so that
541 interoperability between prefixing and nonprefixing of scalar registers
542 is direct and convenient (when the EXTRA field is all zeros).
544 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
549 spec = EXTRA2 << 1 # same as EXTRA3, shifted
551 return (RA << 2) | spec[1:2]
553 return (spec[1:2] << 5) | RA
555 Future versions may extend to 256 by shifting Vector numbering up.
556 Scalar will not be altered.
558 Note that in some cases the range of starting points for Vectors
563 If EXTRA3 is zero, maps to
564 "scalar identity" (scalar OpenPOWER ISA field naming).
566 Fields are as follows:
569 * Mode: register is tagged as scalar or vector
570 * Range/Inc: the range of registers accessible from this EXTRA
571 encoding, and the "increment" (accessibility). "/4" means
572 that this EXTRA encoding may only give access (starting point)
574 * MSB..LSB: the bit field showing how the register opcode field
575 combines with EXTRA to give (extend) the register number (GPR)
577 | Value | Mode | Range/Inc | 6..0 |
578 |-----------|-------|---------------|---------------------|
579 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
580 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
581 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
582 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
583 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
584 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
585 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
586 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
590 If EXTRA2 is zero will map to
591 "scalar identity behaviour" i.e Scalar OpenPOWER register naming:
593 | Value | Mode | Range/inc | 6..0 |
594 |-----------|-------|---------------|-----------|
595 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
596 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
597 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
598 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
602 CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
603 Note that Vectors may only start from CR0, CR4, CR8, CR12, CR16...
605 Encoding shown MSB down to LSB
607 For a 5-bit operand (BA, BB, BT):
609 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
610 |-------|------|---------------|-----------| --------|---------|
611 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
612 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
613 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
614 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
615 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
616 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
617 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
618 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
620 For a 3-bit operand (e.g. BFA):
622 | Value | Mode | Range/Inc | 6..3 | 2..0 |
623 |-------|------|---------------|-----------| --------|
624 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
625 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
626 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
627 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
628 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
629 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
630 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
631 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
635 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
636 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
639 Encoding shown MSB down to LSB
641 For a 5-bit operand (BA, BB, BC):
643 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
644 |-------|--------|----------------|---------|---------|---------|
645 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
646 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
647 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
648 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
650 For a 3-bit operand (e.g. BFA):
652 | Value | Mode | Range/Inc | 6..3 | 2..0 |
653 |-------|------|---------------|-----------| --------|
654 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
655 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
656 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
657 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
661 Now at its own page: [[svp64/appendix]]