3 # SVP64 for OpenPOWER ISA v3.0B
7 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
11 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
12 * [[svp64/discussion]]
14 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
25 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
27 The plan is to create an encoding for SVP64, then to create an encoding
28 for SVP48, then to reorganize them both to improve field overlap,
29 reducing the amount of decoder hardware necessary.
31 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
32 and counting up as you move to the LSB end). All bit ranges are inclusive
33 (so `4:6` means bits 4, 5, and 6).
35 64-bit instructions are split into two 32-bit words, the prefix and the
36 suffix. The prefix always comes before the suffix in PC order.
39 |--------|--------------|--------------|
40 | EXT01 | v3.1 Prefix | v3.1 Suffix |
42 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
44 ## SVP64 encoding features
46 A number of features need to be compacted into a very small space of only 24 bits:
48 * Independent per-register Scalar/Vector tagging and range extension on every register
49 * Element width overrides on both source and destination
50 * Predication on both source and destination
51 * Two different *types* of predication: INT and CR
52 * SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
53 predicate-result mode.
55 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
57 # Definition of Reserved in this spec.
59 For the new fields added in SVP64, instructions that have any of their
60 fields set to a reserved value must cause an illegal instruction trap,
61 to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
63 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
67 SVP64 is designed so that when the prefix is all zeros, and
69 influence occurs (no augmentation) such that all standard OpenPOWER
70 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
72 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
73 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
75 The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
77 # Register Naming and size
79 SV Registers are simply the INT, FP and CR register files extended
80 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
82 Where the integer regfile in standard scalar
83 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
84 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
85 extended to 128 entries, CR0 thru CR127.
87 The names of the registers therefore reflects a simple linear extension
88 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
89 would be reflected by a linear increase in the size of the underlying
90 SRAM used for the regfiles.
92 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
93 so that the register fields are identical to as if SV was not in effect
94 i.e. under these circumstances (EXTRA=0) the register field names RA,
95 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
96 `scalar identity behaviour` described above.
100 With the way that EXTRA fields are defined and applied to register fields,
101 future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
102 requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
104 # Remapped Encoding (`RM[0:23]`)
106 To allow relatively easy remapping of which portions of the Prefix Opcode
107 Map are used for SVP64 without needing to rewrite a large portion of the
108 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
109 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
112 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
113 is defined in the Prefix Fields section.
115 ## Prefix Opcode Map (64-bit instruction encoding)
117 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
119 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
120 empty spaces are yet-to-be-allocated Illegal Instructions.
122 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
123 |------|--------|--------|--------|--------|--------|--------|--------|--------|
124 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
125 |001---| | | | | | | | |
126 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
127 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
128 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
129 |101---| | | | | | | | |
130 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
131 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
133 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
137 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
138 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
139 This is achieved by setting bits 7 and 9 to 1:
141 | Name | Bits | Value | Description |
142 |------------|---------|-------|--------------------------------|
143 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
144 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
145 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
146 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
147 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
148 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
150 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
153 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
154 |--------|-------|---|-------|---|----------|
155 | EXT01 | RM | 1 | RM | 1 | RM |
156 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
158 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
159 instruction. That instruction becomes "prefixed" with the SVP context: the
160 Remapped Encoding field (RM).
164 The following fields are common to all Remapped Encodings:
166 | Field Name | Field bits | Description |
167 |------------|------------|----------------------------------------|
168 | MASKMODE | `0` | Execution (predication) Mask Kind |
169 | MASK | `1:3` | Execution Mask |
170 | ELWIDTH | `4:5` | Element Width |
171 | ELWIDTH_SRC | `6:7` | Element Width for Source |
172 | SUBVL | `8:9` | Sub-vector length |
173 | MODE | `19:23` | changes Vector behaviour |
175 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
176 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
177 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
178 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
180 Bits 10 to 18 are further decoded depending on RM category for the instruction.
181 Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
183 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
187 Mode is an augmentation of SV behaviour. Different types of
188 instructions have different needs, similar to Power ISA
189 v3.1 64 bit prefix 8LS and MTRR formats apply to different
190 instruction types. Modes include Reduction, Iteration, arithmetic
191 saturation, and Fail-First. More specific details in each
192 section and in the [[svp64/appendix]]
194 * For condition register operations see [[sv/cr_ops]]
195 * For LD/ST Modes, see [[sv/ldst]].
196 * For Branch modes, see [[sv/branches]]
197 * For arithmetic and logical, see [[sv/normal]]
201 Default behaviour is set to 0b00 so that zeros follow the convention of
202 `scalar identity behaviour`. In this case it means that elwidth overrides
203 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
204 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
205 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
206 states that, again, the behaviour is not to be modified.
208 Only when elwidth is nonzero is the element width overridden to the
209 explicitly required value.
211 ## Elwidth for Integers:
213 | Value | Mnemonic | Description |
214 |-------|----------------|------------------------------------|
215 | 00 | DEFAULT | default behaviour for operation |
216 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
217 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
218 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
220 This encoding is chosen such that the byte width may be computed as `(3-ew)<<8`
222 ## Elwidth for FP Registers:
224 | Value | Mnemonic | Description |
225 |-------|----------------|------------------------------------|
226 | 00 | DEFAULT | default behaviour for FP operation |
227 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
228 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
229 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
232 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
233 is reserved for a future implementation of SV
235 Note that any operation in Power ISA ending in "s" (`fadds`) shall
236 perform its operation at **half** the ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32.
240 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
241 even means. instead it may be possible to use the bits as extra indices
242 (add to EXTRA2/3) to access the full 128 CRs at the bit level. TBD, several ideas
244 The actual width of the CRs cannot be altered: they are 4 bit. Also,
245 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
246 the INT/FP result to which the elwidth override applies, *not* the CR.
247 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
249 As mentioned TBD, this leaves crops etc. to have a meaning defined for
250 elwidth, because these ops are pure explicit CR based.
252 Examples: mfxm may take the extra bits and use them as extra mask bits.
254 Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
258 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
259 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
260 lines up in combination with all other "default is all zeros" behaviour.
262 | Value | Mnemonic | Subvec | Description |
263 |-------|-----------|---------|------------------------|
264 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
265 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
266 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
267 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
269 The SUBVL encoding value may be thought of as an inclusive range of a
270 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
271 this may be considered to be elements 0b00 to 0b01 inclusive.
273 # MASK/MASK_SRC & MASKMODE Encoding
275 TODO: rename MASK_KIND to MASKMODE
277 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
278 types may not be mixed.
280 Special note: to disable predication this field must
281 be set to zero in combination with Integer Predication also being set
282 to 0b000. this has the effect of enabling "all 1s" in the predicate
283 mask, which is equivalent to "not having any predication at all"
284 and consequently, in combination with all other default zeros, fully
285 disables SV (`scalar identity behaviour`).
287 `MASKMODE` may be set to one of 2 values:
289 | Value | Description |
290 |-----------|------------------------------------------------------|
291 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
292 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
294 Integer Twin predication has a second set of 3 bits that uses the same
295 encoding thus allowing either the same register (r3 or r10) to be used
296 for both src and dest, or different regs (one for src, one for dest).
298 Likewise CR based twin predication has a second set of 3 bits, allowing
299 a different test to be applied.
301 Note that it is assumed that Predicate Masks (whether INT or CR)
302 are read *before* the operations proceed. In practice (for CR Fields)
303 this creates an unnecessary block on parallelism. Therefore,
304 it is up to the programmer to ensure that the CR fields used as
305 Predicate Masks are not being written to by any parallel Vector Loop.
306 Doing so results in **UNDEFINED** behaviour, according to the definition
307 outlined in the OpenPOWER v3.0B Specification.
309 Hardware Implementations are therefore free and clear to delay reading
310 of individual CR fields until the actual predicated element operation
311 needs to take place, safe in the knowledge that no programmer will
312 have issued a Vector Instruction where previous elements could have
313 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
315 ## Integer Predication (MASKMODE=0)
317 When the predicate mode bit is zero the 3 bits are interpreted as below.
318 Twin predication has an identical 3 bit field similarly encoded.
320 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
322 | Value | Mnemonic | Element `i` enabled if: |
323 |-------|----------|------------------------------|
324 | 000 | ALWAYS | predicate effectively all 1s |
325 | 001 | 1 << R3 | `i == R3` |
326 | 010 | R3 | `R3 & (1 << i)` is non-zero |
327 | 011 | ~R3 | `R3 & (1 << i)` is zero |
328 | 100 | R10 | `R10 & (1 << i)` is non-zero |
329 | 101 | ~R10 | `R10 & (1 << i)` is zero |
330 | 110 | R30 | `R30 & (1 << i)` is non-zero |
331 | 111 | ~R30 | `R30 & (1 << i)` is zero |
333 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
335 ## CR-based Predication (MASKMODE=1)
337 When the predicate mode bit is one the 3 bits are interpreted as below.
338 Twin predication has an identical 3 bit field similarly encoded.
340 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
342 | Value | Mnemonic | Element `i` is enabled if |
343 |-------|----------|--------------------------|
344 | 000 | lt | `CR[offs+i].LT` is set |
345 | 001 | nl/ge | `CR[offs+i].LT` is clear |
346 | 010 | gt | `CR[offs+i].GT` is set |
347 | 011 | ng/le | `CR[offs+i].GT` is clear |
348 | 100 | eq | `CR[offs+i].EQ` is set |
349 | 101 | ne | `CR[offs+i].EQ` is clear |
350 | 110 | so/un | `CR[offs+i].FU` is set |
351 | 111 | ns/nu | `CR[offs+i].FU` is clear |
353 CR based predication. TODO: select alternate CR for twin predication? see
354 [[discussion]] Overlap of the two CR based predicates must be taken
355 into account, so the starting point for one of them must be suitably
356 high, or accept that for twin predication VL must not exceed the range
357 where overlap will occur, *or* that they use the same starting point
358 but select different *bits* of the same CRs
360 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
362 Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
364 # Extra Remapped Encoding
366 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
368 There are two categories: Single and Twin Predication.
369 Due to space considerations further subdivision of Single Predication
370 is based on whether the number of src operands is 2 or 3.
372 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
373 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
374 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
375 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
376 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
380 | Field Name | Field bits | Description |
381 |------------|------------|----------------------------------------|
382 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
383 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
384 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
385 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
386 | reserved | `18` | reserved |
390 | Field Name | Field bits | Description |
391 |------------|------------|-------------------------------------------|
392 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
393 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
394 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
396 These are for 2 operand 1 dest instructions, such as `add RT, RA,
397 RB`. However also included are unusual instructions with an implicit dest
398 that is identical to its src reg, such as `rlwinmi`.
400 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
401 an alternative destination. With SV however this becomes possible.
402 Therefore, the fact that the dest is implicitly also a src should not
403 mislead: due to the *prefix* they are different SV regs.
405 * `rlwimi RA, RS, ...`
406 * Rsrc1_EXTRA3 applies to RS as the first src
407 * Rsrc2_EXTRA3 applies to RA as the secomd src
408 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
410 With the addition of the EXTRA bits, the three registers
411 each may be *independently* made vector or scalar, and be independently
412 augmented to 7 bits in length.
416 | Field Name | Field bits | Description |
417 |------------|------------|----------------------------|
418 | Rdest_EXTRA3 | `10:12` | extends Rdest |
419 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
420 | MASK_SRC | `16:18` | Execution Mask for Source |
422 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
424 ## RM-2P-2S1D/1S2D/3S
426 The primary purpose for this encoding is for Twin Predication on LOAD
427 and STORE operations. see [[sv/ldst]] for detailed anslysis.
431 | Field Name | Field bits | Description |
432 |------------|------------|----------------------------|
433 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
434 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
435 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
436 | MASK_SRC | `16:18` | Execution Mask for Source |
438 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
439 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
441 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
443 Note also that LD with update indexed, which takes 2 src and 2 dest
444 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
445 Twin Predication. therefore these are treated as RM-2P-2S1D and the
446 src spec for RA is also used for the same RA as a dest.
448 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
452 EXTRA is the means by which two things are achieved:
454 1. Registers are marked as either Vector *or Scalar*
455 2. Register field numbers (limited typically to 5 bit)
456 are extended in range, both for Scalar and Vector.
458 The register files are therefore extended:
460 * INT is extended from r0-31 to 128
461 * FP is extended from fp0-32 to 128
462 * CR is extended from CR0-7 to CR0-127
464 In the following tables register numbers are constructed from the
465 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
466 or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
467 interoperability between prefixing and nonprefixing of scalar registers
468 is direct and convenient (when the EXTRA field is all zeros).
470 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
475 spec = EXTRA2 << 1 # same as EXTRA3, shifted
477 return (RA << 2) | spec[1:2]
479 return (spec[1:2] << 5) | RA
481 Future versions may extend to 256 by shifting Vector numbering up.
482 Scalar will not be altered.
486 alternative which is understandable and, if EXTRA3 is zero, maps to
487 "no effect" (scalar OpenPOWER ISA field naming). also, these are the
488 encodings used in the original SV Prefix scheme. the reason why they
489 were chosen is so that scalar registers in v3.0B and prefixed scalar
490 registers have access to the same 32 registers.
492 Fields are as follows:
495 * Mode: register is tagged as scalar or vector
496 * Range/Inc: the range of registers accessible from this EXTRA
497 encoding, and the "increment" (accessibility). "/4" means
498 that this EXTRA encoding may only give access (starting point)
500 * MSB..LSB: the bit field showing how the register opcode field
501 combines with EXTRA to give (extend) the register number (GPR)
503 | Value | Mode | Range/Inc | 6..0 |
504 |-----------|-------|---------------|---------------------|
505 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
506 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
507 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
508 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
509 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
510 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
511 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
512 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
516 alternative which is understandable and, if EXTRA2 is zero will map to
517 "no effect" i.e Scalar OpenPOWER register naming:
519 | Value | Mode | Range/inc | 6..0 |
520 |-----------|-------|---------------|-----------|
521 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
522 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
523 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
524 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
528 CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
530 Encoding shown MSB down to LSB
532 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
533 |-------|------|---------------|-----------| --------|---------|
534 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
535 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
536 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
537 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
538 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
539 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
540 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
541 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
545 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
547 Encoding shown MSB down to LSB
549 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
550 |-------|--------|----------------|---------|---------|---------|
551 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
552 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
553 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
554 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
558 Now at its own page: [[svp64/appendix]]