openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPOWER Membership
   8   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
   9 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  10 * [[openpower/isatables]]
  11 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  12 * [[openpower/gem5]]
  13 * [[openpower/sv]]
  14 * [[openpower/pearpc]]
  15 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  16 * [[3d_gpu/architecture/decoder]]
  17 * <https://forums.raptorcs.com/>
  18 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  19 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  20 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  21 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  22 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  23
  24 PowerPC Unit Tests
  25
  26 * <https://github.com/lioncash/DolphinPPCTests>
  27 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  28
  29 Summary
  30
  31 * FP32 is converted to FP64. Requires SimpleV to be active.
  32 * FP16 needed
  33 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  34 * FCVT between 16/32/64 needed
  35 * c++11 atomics not very efficient
  36 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  37 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  38
  39 # What we are *NOT* doing:
  40
  41 * A processor that is fundamentally incompatible (noncompliant) with Power.
  42  (**escape-sequencing requires and guarantees compatibility**).
  43 * Opcode 4 Signal Processing (SPE)
  44 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  45 * Avoidable legacy opcodes
  46
  47 # SimpleV
  48
  49 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  50 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  51 register files to "a sequence of elements".  The **one** instruction
  52 (an unmodified **scalar** instruction) is interpreted as a *hardware
  53 for-loop* that issues **multiple** internal instructions with
  54 sequentially-incrementing register numbers.
  55
  56 Thus it is completely unnecessary to add any vector opcodes - at all -
  57 saving hugely on both hardware and compiler development time when
  58 the concept is dropped on top of a pre-existing ISA.
  59
  60 ## Condition Registers
  61
  62 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  63
  64 ## Carry
  65
  66 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  67
  68 # Integer Overflow / Saturate
  69
  70 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  71
  72 # atomics
  73
  74 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  75
  76 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  77
  78 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  79
  80 # FP16
  81
  82 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  83
  84 Usually done with a fmt field, 2 bit, last one is FP128
  85
  86 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  87
  88 # Escape Sequencing
  89
  90 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  91 from OpenPower Foundation.
  92
  93 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  94 (including for and by OpenPower Foundation)
  95
  96 ## Branches in namespaces
  97
  98 Branches are fine as it is up to the compiler to decide whether to let the
  99 ISAMUX/NS/escape-sequence countdown run out.
 100
 101 This is all a software / compiler / ABI issue.
 102
 103 ## Function calls in namespaces
 104
 105 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 106
 107 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 108
 109 All of this is a software issue (compiler / ABI).
 110
 111 # Compressed, 48, 64, VBLOCK
 112
 113 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 114
 115 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 116 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 117
 118 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 119 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 120 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 121 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 122
 123 Note that this requires BE instruction encoding (separate from
 124 data BE/LE encoding).  BE encoding always places the major opcode in
 125 the first 2 bytes of the raw (uninterpreted) sequential instruction
 126 byte stream.
 127
 128 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 129 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 130 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 131
 132 It is not possible to distinguish LE-encoded 32-bit instructions
 133 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 134 instructions, the opcode falls into:
 135
 136 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 137   byte stream for a 32-bit instruction
 138 * bytes 0 and 1 for a 16-bit Compressed instruction
 139 * bytes 4 and 5 for a 48-bit SVP P48
 140 * bytes 6 and 7 for a 64-bit SVP P64
 141
 142 Clearly this is an impossible situation, therefore BE is the only
 143 option.  Note: *this is completely separate from BE/LE for data*
 144
 145 # Compressed 16
 146
 147 Further "escape-sequencing".
 148
 149 Only 11 bits available. Idea: have "pages" where one instruction selects
 150 the page number. It also specifies for how long that page is activated
 151 (terminated on a branch)
 152
 153 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 154
 155 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 156
 157 Store activation length in a CSR.
 158
 159 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 160
 161 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 162
 163 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 164
 165 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 166
 167 # RISCV userspace
 168
 169 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 170
 171 the exception entry point:
 172 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 173
 174 the rest of the context switch code is in a different file:
 175 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>