openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPOWER Membership
   8   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
   9 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  10 * [[openpower/isatables]]
  11 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  12 * [[openpower/gem5]]
  13 * [[openpower/sv]]
  14 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  15 * [[openpower/pearpc]]
  16 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  17 * [[3d_gpu/architecture/decoder]]
  18 * <https://forums.raptorcs.com/>
  19 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  20 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  21 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  22 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  23 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  24
  25 PowerPC Unit Tests
  26
  27 * <https://github.com/lioncash/DolphinPPCTests>
  28 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  29
  30 Summary
  31
  32 * FP32 is converted to FP64. Requires SimpleV to be active.
  33 * FP16 needed
  34 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  35 * FCVT between 16/32/64 needed
  36 * c++11 atomics not very efficient
  37 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  38 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  39
  40 # What we are *NOT* doing:
  41
  42 * A processor that is fundamentally incompatible (noncompliant) with Power.
  43  (**escape-sequencing requires and guarantees compatibility**).
  44 * Opcode 4 Signal Processing (SPE)
  45 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  46 * Avoidable legacy opcodes
  47
  48 # SimpleV
  49
  50 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  51 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  52 register files to "a sequence of elements".  The **one** instruction
  53 (an unmodified **scalar** instruction) is interpreted as a *hardware
  54 for-loop* that issues **multiple** internal instructions with
  55 sequentially-incrementing register numbers.
  56
  57 Thus it is completely unnecessary to add any vector opcodes - at all -
  58 saving hugely on both hardware and compiler development time when
  59 the concept is dropped on top of a pre-existing ISA.
  60
  61 ## Condition Registers
  62
  63 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  64
  65 ## Carry
  66
  67 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  68
  69 # Integer Overflow / Saturate
  70
  71 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  72
  73 # atomics
  74
  75 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  76
  77 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  78
  79 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  80
  81 # FP16
  82
  83 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  84
  85 Usually done with a fmt field, 2 bit, last one is FP128
  86
  87 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  88
  89 # Escape Sequencing
  90
  91 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  92 from OpenPower Foundation.
  93
  94 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  95 (including for and by OpenPower Foundation)
  96
  97 ## Branches in namespaces
  98
  99 Branches are fine as it is up to the compiler to decide whether to let the
 100 ISAMUX/NS/escape-sequence countdown run out.
 101
 102 This is all a software / compiler / ABI issue.
 103
 104 ## Function calls in namespaces
 105
 106 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 107
 108 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 109
 110 All of this is a software issue (compiler / ABI).
 111
 112 # Compressed, 48, 64, VBLOCK
 113
 114 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 115
 116 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 117 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 118
 119 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 120 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 121 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 122 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 123
 124 Note that this requires BE instruction encoding (separate from
 125 data BE/LE encoding).  BE encoding always places the major opcode in
 126 the first 2 bytes of the raw (uninterpreted) sequential instruction
 127 byte stream.
 128
 129 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 130 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 131 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 132
 133 It is not possible to distinguish LE-encoded 32-bit instructions
 134 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 135 instructions, the opcode falls into:
 136
 137 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 138   byte stream for a 32-bit instruction
 139 * bytes 0 and 1 for a 16-bit Compressed instruction
 140 * bytes 4 and 5 for a 48-bit SVP P48
 141 * bytes 6 and 7 for a 64-bit SVP P64
 142
 143 Clearly this is an impossible situation, therefore BE is the only
 144 option.  Note: *this is completely separate from BE/LE for data*
 145
 146 # Compressed 16
 147
 148 Further "escape-sequencing".
 149
 150 Only 11 bits available. Idea: have "pages" where one instruction selects
 151 the page number. It also specifies for how long that page is activated
 152 (terminated on a branch)
 153
 154 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 155
 156 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 157
 158 Store activation length in a CSR.
 159
 160 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 161
 162 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 163
 164 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 165
 166 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 167
 168 # RISCV userspace
 169
 170 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 171
 172 the exception entry point:
 173 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 174
 175 the rest of the context switch code is in a different file:
 176 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>