openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPOWER Membership
   8   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
   9 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  10 * [[openpower/isatables]]
  11 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  12 * [[openpower/gem5]]
  13 * [[openpower/sv]]
  14 * [[openpower/simd_vsx]]
  15 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  16 * [[openpower/pearpc]]
  17 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  18 * [[3d_gpu/architecture/decoder]]
  19 * <https://forums.raptorcs.com/>
  20 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  21 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  22 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  23 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  24 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  25
  26 PowerPC Unit Tests
  27
  28 * <https://github.com/lioncash/DolphinPPCTests>
  29 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  30
  31 Summary
  32
  33 * FP32 is converted to FP64. Requires SimpleV to be active.
  34 * FP16 needed
  35 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  36 * FCVT between 16/32/64 needed
  37 * c++11 atomics not very efficient
  38 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  39 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  40
  41 # What we are *NOT* doing:
  42
  43 * A processor that is fundamentally incompatible (noncompliant) with Power.
  44  (**escape-sequencing requires and guarantees compatibility**).
  45 * Opcode 4 Signal Processing (SPE)
  46 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  47 * Avoidable legacy opcodes
  48
  49 # SimpleV
  50
  51 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  52 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  53 register files to "a sequence of elements".  The **one** instruction
  54 (an unmodified **scalar** instruction) is interpreted as a *hardware
  55 for-loop* that issues **multiple** internal instructions with
  56 sequentially-incrementing register numbers.
  57
  58 Thus it is completely unnecessary to add any vector opcodes - at all -
  59 saving hugely on both hardware and compiler development time when
  60 the concept is dropped on top of a pre-existing ISA.
  61
  62 ## Condition Registers
  63
  64 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  65
  66 ## Carry
  67
  68 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  69
  70 # Integer Overflow / Saturate
  71
  72 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  73
  74 # atomics
  75
  76 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  77
  78 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  79
  80 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  81
  82 # FP16
  83
  84 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  85
  86 Usually done with a fmt field, 2 bit, last one is FP128
  87
  88 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  89
  90 # Escape Sequencing
  91
  92 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  93 from OpenPower Foundation.
  94
  95 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  96 (including for and by OpenPower Foundation)
  97
  98 ## Branches in namespaces
  99
 100 Branches are fine as it is up to the compiler to decide whether to let the
 101 ISAMUX/NS/escape-sequence countdown run out.
 102
 103 This is all a software / compiler / ABI issue.
 104
 105 ## Function calls in namespaces
 106
 107 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 108
 109 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 110
 111 All of this is a software issue (compiler / ABI).
 112
 113 # Compressed, 48, 64, VBLOCK
 114
 115 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 116
 117 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 118 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 119
 120 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 121 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 122 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 123 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 124
 125 Note that this requires BE instruction encoding (separate from
 126 data BE/LE encoding).  BE encoding always places the major opcode in
 127 the first 2 bytes of the raw (uninterpreted) sequential instruction
 128 byte stream.
 129
 130 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 131 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 132 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 133
 134 It is not possible to distinguish LE-encoded 32-bit instructions
 135 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 136 instructions, the opcode falls into:
 137
 138 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 139   byte stream for a 32-bit instruction
 140 * bytes 0 and 1 for a 16-bit Compressed instruction
 141 * bytes 4 and 5 for a 48-bit SVP P48
 142 * bytes 6 and 7 for a 64-bit SVP P64
 143
 144 Clearly this is an impossible situation, therefore BE is the only
 145 option.  Note: *this is completely separate from BE/LE for data*
 146
 147 # Compressed 16
 148
 149 Further "escape-sequencing".
 150
 151 Only 11 bits available. Idea: have "pages" where one instruction selects
 152 the page number. It also specifies for how long that page is activated
 153 (terminated on a branch)
 154
 155 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 156
 157 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 158
 159 Store activation length in a CSR.
 160
 161 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 162
 163 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 164
 165 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 166
 167 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 168
 169 # RISCV userspace
 170
 171 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 172
 173 the exception entry point:
 174 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 175
 176 the rest of the context switch code is in a different file:
 177 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>