openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * [[openpower/gem5]]
  10 * [[openpower/pearpc]]
  11 * [[3d_gpu/architecture/decoder]]
  12 * <https://forums.raptorcs.com/>
  13 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  14 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  15 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  16 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  17 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  18
  19 PowerPC Unit Tests
  20
  21 * <https://github.com/lioncash/DolphinPPCTests>
  22 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  23
  24 Summary
  25
  26 * FP32 is converted to FP64. Requires SimpleV to be active.
  27 * FP16 needed
  28 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  29 * FCVT between 16/32/64 needed
  30 * c++11 atomics not very efficient
  31 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  32 * needs escape sequencing (ISAMUX/NS)
  33
  34 # What we are *NOT* doing:
  35
  36 * A processor that is fundamentally incompatible (noncompliant) with Power.
  37  (**escape-sequencing requires and guarantees compatibility**).
  38 * Opcode 4 Signal Processing (SPE)
  39 * Opcode 4 Vectors or Opcode 60 VSX
  40 * Avoidable legacy opcodes
  41
  42 # SimpleV
  43
  44 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  45 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  46 register files to "a sequence of elements".  The **one** instruction
  47 (an unmodified **scalar** instruction) is interpreted as a *hardware
  48 for-loop* that issues **multiple** internal instructions with
  49 sequentially-incrementing register numbers.
  50
  51 Thus it is completely unnecessary to add any vector opcodes - at all -
  52 saving hugely on both hardware and compiler development time when
  53 the concept is dropped on top of a pre-existing ISA.
  54
  55 ## Condition Registers
  56
  57 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  58
  59 ## Carry
  60
  61 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  62
  63 # Integer Overflow / Saturate
  64
  65 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  66
  67 # atomics
  68
  69 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  70
  71 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  72
  73 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  74
  75 # FP16
  76
  77 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  78
  79 Usually done with a fmt field, 2 bit, last one is FP128
  80
  81 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  82
  83 # Escape Sequencing
  84
  85 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  86 from OpenPower Foundation.
  87
  88 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  89 (including for and by OpenPower Foundation)
  90
  91 ## Branches in namespaces
  92
  93 Branches are fine as it is up to the compiler to decide whether to let the
  94 ISAMUX/NS/escape-sequence countdown run out.
  95
  96 This is all a software / compiler / ABI issue.
  97
  98 ## Function calls in namespaces
  99
 100 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 101
 102 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 103
 104 All of this is a software issue (compiler / ABI).
 105
 106 # Compressed, 48, 64, VBLOCK
 107
 108 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 109
 110 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 111 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 112
 113 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 114 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 115 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 116 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 117
 118 # Compressed 16
 119
 120 Further "escape-sequencing".
 121
 122 Only 11 bits available. Idea: have "pages" where one instruction selects
 123 the page number. It also specifies for how long that page is activated
 124 (terminated on a branch)
 125
 126 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 127
 128 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 129
 130 Store activation length in a CSR.
 131
 132 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 133
 134 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 135
 136 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 137
 138 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 139
 140 # RISCV userspace
 141
 142 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 143
 144 the exception entry point:
 145 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 146
 147 the rest of the context switch code is in a different file:
 148 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589