openpower.mdwn

   1 # OpenPOWER
   2
   3 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
   4 This evolved to a specification known as the OpenPOWER ISA. In 2019 IBM made the OpenPOWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors
   5 happen to implement what is now known as the OpenPOWER ISA. The names
   6 POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel
   7 i5, i7, i9 etc. and are frequently conflated with versions of the OpenPOWER ISA (v2.08, v3.0, v3.1).
   8
   9 Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER, thanks to IBM's involvement,
  10 is designed for high performance.
  11
  12 # Evaluation
  13
  14 EULA released! looks good.
  15
  16 Links
  17
  18 * OpenPOWER Membership
  19   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
  20 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  21 * [[openpower/isatables]]
  22 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  23 * [[openpower/gem5]]
  24 * [[openpower/sv]]
  25 * [[openpower/simd_vsx]]
  26 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  27 * [[openpower/pearpc]]
  28 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  29 * [[3d_gpu/architecture/decoder]]
  30 * <https://forums.raptorcs.com/>
  31 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  32 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  33 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  34 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  35 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  36
  37 PowerPC Unit Tests
  38
  39 * <https://github.com/lioncash/DolphinPPCTests>
  40 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  41
  42 Summary
  43
  44 * FP32 is converted to FP64. Requires SimpleV to be active.
  45 * FP16 needed
  46 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  47 * FCVT between 16/32/64 needed
  48 * c++11 atomics not very efficient
  49 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  50 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  51
  52 # What we are *NOT* doing:
  53
  54 * A processor that is fundamentally incompatible (noncompliant) with Power.
  55  (**escape-sequencing requires and guarantees compatibility**).
  56 * Opcode 4 Signal Processing (SPE)
  57 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  58 * Avoidable legacy opcodes
  59
  60 # SimpleV
  61
  62 see [[openpower/sv]].
  63 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  64 register files to "a sequence of elements".  The **one** instruction
  65 (an unmodified **scalar** instruction) is interpreted as a *hardware
  66 for-loop* that issues **multiple** internal instructions with
  67 sequentially-incrementing register numbers.
  68
  69 Thus it is completely unnecessary to add any vector opcodes - at all -
  70 saving hugely on both hardware and compiler development time when
  71 the concept is dropped on top of a pre-existing ISA.
  72
  73 ## Condition Registers
  74
  75 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  76
  77 ## Carry
  78
  79 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
  80
  81 # Integer Overflow / Saturate
  82
  83 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  84
  85 # atomics
  86
  87 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  88
  89 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  90
  91 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  92
  93 # FP16
  94
  95 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  96
  97 Usually done with a fmt field, 2 bit, last one is FP128
  98
  99 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
 100
 101 # Escape Sequencing
 102
 103 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
 104 from OpenPower Foundation.
 105
 106 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 107 (including for and by OpenPower Foundation)
 108
 109 ## Branches in namespaces
 110
 111 Branches are fine as it is up to the compiler to decide whether to let the
 112 ISAMUX/NS/escape-sequence countdown run out.
 113
 114 This is all a software / compiler / ABI issue.
 115
 116 ## Function calls in namespaces
 117
 118 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 119
 120 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 121
 122 All of this is a software issue (compiler / ABI).
 123
 124 # Compressed, 48, 64, VBLOCK
 125
 126 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 127
 128 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 129 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 130
 131 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 132 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 133 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 134 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 135
 136 Note that this requires BE instruction encoding (separate from
 137 data BE/LE encoding).  BE encoding always places the major opcode in
 138 the first 2 bytes of the raw (uninterpreted) sequential instruction
 139 byte stream.
 140
 141 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 142 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 143 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 144
 145 It is not possible to distinguish LE-encoded 32-bit instructions
 146 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 147 instructions, the opcode falls into:
 148
 149 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 150   byte stream for a 32-bit instruction
 151 * bytes 0 and 1 for a 16-bit Compressed instruction
 152 * bytes 4 and 5 for a 48-bit SVP P48
 153 * bytes 6 and 7 for a 64-bit SVP P64
 154
 155 Clearly this is an impossible situation, therefore BE is the only
 156 option.  Note: *this is completely separate from BE/LE for data*
 157
 158 # Compressed 16
 159
 160 Further "escape-sequencing".
 161
 162 Only 11 bits available. Idea: have "pages" where one instruction selects
 163 the page number. It also specifies for how long that page is activated
 164 (terminated on a branch)
 165
 166 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 167
 168 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 169
 170 Store activation length in a CSR.
 171
 172 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 173
 174 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 175
 176 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 177
 178 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 179