openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * <https://forums.raptorcs.com/>
  10 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  11 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  12 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  13 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  14 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  15
  16 Summary
  17
  18 * FP32 is converted to FP64. Requires SimpleV to be active.
  19 * FP16 needed
  20 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  21 * FCVT between 16/32/64 needed
  22 * c++11 atomics not very efficient
  23 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  24 * needs escape sequencing (ISAMUX/NS)
  25
  26 # What we are *NOT* doing:
  27
  28 * A processor that is fundamentally incompatible (noncompliant) with Power.
  29  (**escape-sequencing requires and guarantees compatibility**).
  30 * Opcode 4 Signal Processing (SPE)
  31 * Opcode 4 Vectors or Opcode 60 VSX
  32 * Avoidable legacy opcodes
  33
  34 # SimpleV
  35
  36 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  37 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  38 register files to "a sequence of elements".  The **one** instruction
  39 (an unmodified **scalar** instruction) is interpreted as a *hardware
  40 for-loop* that issues **multiple** internal instructions with
  41 sequentially-incrementing register numbers.
  42
  43 Thus it is completely unnecessary to add any vector opcodes - at all -
  44 saving hugely on both hardware and compiler development time when
  45 the concept is dropped on top of a pre-existing ISA.
  46
  47 ## Condition Registers
  48
  49 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  50
  51 # Integer Overflow / Saturate
  52
  53 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  54
  55 # atomics
  56
  57 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  58
  59 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  60
  61 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  62
  63 # FP16
  64
  65 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  66
  67 Usually done with a fmt field, 2 bit, last one is FP128
  68
  69 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  70
  71 # Escape Sequencing
  72
  73 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  74 from OpenPower Foundation.
  75
  76 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  77 (including for and by OpenPower Foundation)
  78
  79 ## Branches in namespaces
  80
  81 Branches are fine as it is up to the compiler to decide whether to let the
  82 ISAMUX/NS/escape-sequence countdown run out.
  83
  84 This is all a software / compiler / ABI issue.
  85
  86 ## Function calls in namespaces
  87
  88 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  89
  90 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  91
  92 All of this is a software issue (compiler / ABI).
  93
  94 # Compressed, 48, 64, VBLOCK
  95
  96 TODO investigate Power VLE (Freescale doc Ref 314-68105)
  97
  98 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
  99 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 100
 101 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 102 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 103 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 104 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 105
 106 # Compressed 16
 107
 108 Further "escape-sequencing".
 109
 110 Only 11 bits available. Idea: have "pages" where one instruction selects
 111 the page number. It also specifies for how long that page is activated
 112 (terminated on a branch)
 113
 114 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 115
 116 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 117
 118 Store activation length in a CSR.
 119
 120 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 121
 122 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 123
 124 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 125
 126 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 127
 128 # RISCV userspace
 129
 130 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 131
 132 the exception entry point:
 133 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 134
 135 the rest of the context switch code is in a different file:
 136 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589