openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  10 * [[openpower/gem5]]
  11 * [[openpower/pearpc]]
  12 * [[3d_gpu/architecture/decoder]]
  13 * <https://forums.raptorcs.com/>
  14 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  15 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  16 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  17 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  18 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  19
  20 PowerPC Unit Tests
  21
  22 * <https://github.com/lioncash/DolphinPPCTests>
  23 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  24
  25 Summary
  26
  27 * FP32 is converted to FP64. Requires SimpleV to be active.
  28 * FP16 needed
  29 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  30 * FCVT between 16/32/64 needed
  31 * c++11 atomics not very efficient
  32 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  33 * needs escape sequencing (ISAMUX/NS)
  34
  35 # What we are *NOT* doing:
  36
  37 * A processor that is fundamentally incompatible (noncompliant) with Power.
  38  (**escape-sequencing requires and guarantees compatibility**).
  39 * Opcode 4 Signal Processing (SPE)
  40 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  41 * Avoidable legacy opcodes
  42
  43 # SimpleV
  44
  45 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  46 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  47 register files to "a sequence of elements".  The **one** instruction
  48 (an unmodified **scalar** instruction) is interpreted as a *hardware
  49 for-loop* that issues **multiple** internal instructions with
  50 sequentially-incrementing register numbers.
  51
  52 Thus it is completely unnecessary to add any vector opcodes - at all -
  53 saving hugely on both hardware and compiler development time when
  54 the concept is dropped on top of a pre-existing ISA.
  55
  56 ## Condition Registers
  57
  58 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  59
  60 ## Carry
  61
  62 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  63
  64 # Integer Overflow / Saturate
  65
  66 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  67
  68 # atomics
  69
  70 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  71
  72 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  73
  74 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  75
  76 # FP16
  77
  78 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  79
  80 Usually done with a fmt field, 2 bit, last one is FP128
  81
  82 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  83
  84 # Escape Sequencing
  85
  86 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  87 from OpenPower Foundation.
  88
  89 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  90 (including for and by OpenPower Foundation)
  91
  92 ## Branches in namespaces
  93
  94 Branches are fine as it is up to the compiler to decide whether to let the
  95 ISAMUX/NS/escape-sequence countdown run out.
  96
  97 This is all a software / compiler / ABI issue.
  98
  99 ## Function calls in namespaces
 100
 101 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 102
 103 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 104
 105 All of this is a software issue (compiler / ABI).
 106
 107 # Compressed, 48, 64, VBLOCK
 108
 109 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 110
 111 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 112 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 113
 114 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 115 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 116 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 117 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 118
 119 Note that this requires BE instruction encoding (separate from
 120 data BE/LE encoding).  BE encoding always places the major opcode in
 121 the first 2 bytes of the raw (uninterpreted) sequential instruction
 122 byte stream.
 123
 124 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 125 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 126 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 127
 128 It is not possible to distinguish LE-encoded 32-bit instructions
 129 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 130 instructions, the opcode falls into:
 131
 132 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 133   byte stream for a 32-bit instruction
 134 * bytes 0 and 1 for a 16-bit Compressed instruction
 135 * bytes 4 and 5 for a 48-bit SVP P48
 136 * bytes 6 and 7 for a 64-bit SVP P64
 137
 138 Clearly this is an impossible situation, therefore BE is the only
 139 option.  Note: *this is completely separate from BE/LE for data*
 140
 141 # Compressed 16
 142
 143 Further "escape-sequencing".
 144
 145 Only 11 bits available. Idea: have "pages" where one instruction selects
 146 the page number. It also specifies for how long that page is activated
 147 (terminated on a branch)
 148
 149 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 150
 151 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 152
 153 Store activation length in a CSR.
 154
 155 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 156
 157 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 158
 159 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 160
 161 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 162
 163 # RISCV userspace
 164
 165 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 166
 167 the exception entry point:
 168 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 169
 170 the rest of the context switch code is in a different file:
 171 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589